Lines Matching defs:dev_priv
41 dev_priv,
46 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
66 if (radeon_check_offset(dev_priv, off))
73 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
80 off = off - fb_end - 1 + dev_priv->gart_vm_start;
83 if (radeon_check_offset(dev_priv, off)) {
92 dev_priv,
99 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
107 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
120 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
130 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
145 if (radeon_check_and_fixup_offset(dev_priv,
161 if (radeon_check_and_fixup_offset(dev_priv,
266 dev_priv,
307 if (dev_priv->microcode_version != UCODE_R200) {
328 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) {
339 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[i])) {
358 if (dev_priv->microcode_version != UCODE_R100) {
362 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[1])) {
369 if (dev_priv->microcode_version != UCODE_R200) {
377 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &cmd[2])) {
391 (dev_priv, filp_priv, &offset)) {
402 (dev_priv, filp_priv, &offset)) {
422 static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
440 static int radeon_emit_state(drm_radeon_private_t * dev_priv,
450 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
456 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
545 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
565 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
585 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
609 static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
623 return radeon_emit_state(dev_priv, filp_priv, &state->context,
740 static void radeon_clear_box(drm_radeon_private_t * dev_priv,
746 x += dev_priv->sarea_priv->boxes[0].x1;
747 y += dev_priv->sarea_priv->boxes[0].y1;
749 switch (dev_priv->color_fmt) {
771 (dev_priv->color_fmt << 8) |
775 if (dev_priv->sarea_priv->pfCurrentPage == 1) {
776 OUT_RING(dev_priv->front_pitch_offset);
778 OUT_RING(dev_priv->back_pitch_offset);
789 static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
794 if (dev_priv->stats.last_frame_reads > 1 ||
795 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
796 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
799 if (dev_priv->stats.freelist_loops) {
800 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
805 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
806 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
810 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
811 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
818 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
819 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
823 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
824 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
829 if (dev_priv->stats.requested_bufs) {
830 if (dev_priv->stats.requested_bufs > 100)
831 dev_priv->stats.requested_bufs = 100;
833 radeon_clear_box(dev_priv, 4, 16,
834 dev_priv->stats.requested_bufs, 4,
838 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
850 drm_radeon_private_t *dev_priv = dev->dev_private;
851 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
852 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
861 dev_priv->stats.clears++;
863 if (dev_priv->sarea_priv->pfCurrentPage == 1) {
889 dev_priv->sarea_priv->ctx_owner = 0;
907 (dev_priv->
913 OUT_RING(dev_priv->front_pitch_offset);
929 (dev_priv->
935 OUT_RING(dev_priv->back_pitch_offset);
953 dev_priv->depth_fmt ==
954 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
955 2) : (dev_priv->
966 dev_priv->sarea_priv->ctx_owner = 0;
968 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1009 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1010 && !(dev_priv->microcode_version == UCODE_R200)) {
1032 } else if (dev_priv->microcode_version == UCODE_R200) {
1086 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1087 && (dev_priv->microcode_version == UCODE_R200)
1104 else if ((dev_priv->microcode_version == UCODE_R200) &&
1199 dev_priv->sarea_priv->ctx_owner = 0;
1206 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1270 dev_priv->sarea_priv->ctx_owner = 0;
1277 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1313 dev_priv->sarea_priv->last_clear++;
1317 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1325 drm_radeon_private_t *dev_priv = dev->dev_private;
1326 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1335 if (dev_priv->do_boxes)
1336 radeon_cp_performance_boxes(dev_priv);
1361 (dev_priv->color_fmt << 8) |
1370 if (dev_priv->sarea_priv->pfCurrentPage == 0) {
1371 OUT_RING(dev_priv->back_pitch_offset);
1372 OUT_RING(dev_priv->front_pitch_offset);
1374 OUT_RING(dev_priv->front_pitch_offset);
1375 OUT_RING(dev_priv->back_pitch_offset);
1390 dev_priv->sarea_priv->last_frame++;
1394 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1402 drm_radeon_private_t *dev_priv = dev->dev_private;
1403 drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
1404 int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
1405 ? dev_priv->front_offset : dev_priv->back_offset;
1409 dev_priv->sarea_priv->pfCurrentPage);
1413 if (dev_priv->do_boxes) {
1414 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1415 radeon_cp_performance_boxes(dev_priv);
1424 ((sarea->frame.y * dev_priv->front_pitch +
1425 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1427 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1436 dev_priv->sarea_priv->last_frame++;
1437 dev_priv->sarea_priv->pfCurrentPage =
1438 1 - dev_priv->sarea_priv->pfCurrentPage;
1442 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1483 drm_radeon_private_t *dev_priv = dev->dev_private;
1484 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1485 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1504 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1527 drm_radeon_private_t *dev_priv = dev->dev_private;
1531 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1545 drm_radeon_private_t *dev_priv = dev->dev_private;
1550 int offset = (dev_priv->gart_buffers_offset
1580 drm_radeon_private_t *dev_priv = dev->dev_private;
1581 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1582 int offset = dev_priv->gart_buffers_offset + prim->offset;
1622 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1639 drm_radeon_private_t *dev_priv = dev->dev_private;
1654 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1659 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1742 radeon_do_cp_idle(dev_priv);
1831 offset = dev_priv->gart_buffers_offset + buf->offset;
1871 drm_radeon_private_t *dev_priv = dev->dev_private;
1890 drm_radeon_private_t *dev_priv)
1892 if (!dev_priv->mmio)
1895 radeon_do_cp_idle(dev_priv);
1898 dev_priv->surfaces[surf_index].flags);
1900 dev_priv->surfaces[surf_index].lower);
1902 dev_priv->surfaces[surf_index].upper);
1917 drm_radeon_private_t *dev_priv, DRMFILE filp)
1936 if ((dev_priv->surfaces[i].refcount != 0) &&
1937 (((new_lower >= dev_priv->surfaces[i].lower) &&
1938 (new_lower < dev_priv->surfaces[i].upper)) ||
1939 ((new_lower < dev_priv->surfaces[i].lower) &&
1940 (new_upper > dev_priv->surfaces[i].lower)))) {
1947 if (dev_priv->virt_surfaces[i].filp == 0)
1957 if ((dev_priv->surfaces[i].refcount == 1) &&
1958 (new->flags == dev_priv->surfaces[i].flags) &&
1959 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1960 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1966 dev_priv->surfaces[i].refcount++;
1967 dev_priv->surfaces[i].lower = s->lower;
1968 radeon_apply_surface_regs(s->surface_index, dev_priv);
1973 if ((dev_priv->surfaces[i].refcount == 1) &&
1974 (new->flags == dev_priv->surfaces[i].flags) &&
1975 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1976 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1982 dev_priv->surfaces[i].refcount++;
1983 dev_priv->surfaces[i].upper = s->upper;
1984 radeon_apply_surface_regs(s->surface_index, dev_priv);
1991 if (dev_priv->surfaces[i].refcount == 0) {
1992 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1998 dev_priv->surfaces[i].refcount = 1;
1999 dev_priv->surfaces[i].lower = s->lower;
2000 dev_priv->surfaces[i].upper = s->upper;
2001 dev_priv->surfaces[i].flags = s->flags;
2002 radeon_apply_surface_regs(s->surface_index, dev_priv);
2011 static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
2018 s = &(dev_priv->virt_surfaces[i]);
2021 if (dev_priv->surfaces[s->surface_index].
2023 dev_priv->surfaces[s->surface_index].
2026 if (dev_priv->surfaces[s->surface_index].
2028 dev_priv->surfaces[s->surface_index].
2031 dev_priv->surfaces[s->surface_index].refcount--;
2032 if (dev_priv->surfaces[s->surface_index].
2034 dev_priv->surfaces[s->surface_index].
2038 dev_priv);
2047 drm_radeon_private_t * dev_priv)
2051 if (dev_priv->virt_surfaces[i].filp == filp)
2052 free_surface(filp, dev_priv,
2053 dev_priv->virt_surfaces[i].lower);
2063 drm_radeon_private_t *dev_priv = dev->dev_private;
2070 if (alloc_surface(&alloc, dev_priv, filp) == -1)
2079 drm_radeon_private_t *dev_priv = dev->dev_private;
2085 if (free_surface(filp, dev_priv, memfree.address))
2094 drm_radeon_private_t *dev_priv = dev->dev_private;
2095 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2105 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2124 drm_radeon_private_t *dev_priv = dev->dev_private;
2139 dev_priv->page_flipping = 1;
2141 if (dev_priv->sarea_priv->pfCurrentPage != 1)
2142 dev_priv->sarea_priv->pfCurrentPage = 0;
2153 drm_radeon_private_t *dev_priv = dev->dev_private;
2158 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2160 if (!dev_priv->page_flipping)
2172 drm_radeon_private_t *dev_priv = dev->dev_private;
2173 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2178 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2184 dev_priv->sarea_priv->ctx_owner = 0;
2193 drm_radeon_private_t *dev_priv = dev->dev_private;
2195 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2221 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2222 VB_AGE_TEST_WITH_RETURN(dev_priv);
2242 if (radeon_emit_state(dev_priv, filp_priv,
2260 prim.vc_format = dev_priv->sarea_priv->vc_format;
2276 drm_radeon_private_t *dev_priv = dev->dev_private;
2278 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2305 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2306 VB_AGE_TEST_WITH_RETURN(dev_priv);
2335 if (radeon_emit_state(dev_priv, filp_priv,
2356 prim.vc_format = dev_priv->sarea_priv->vc_format;
2370 drm_radeon_private_t *dev_priv = dev->dev_private;
2390 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2391 VB_AGE_TEST_WITH_RETURN(dev_priv);
2402 drm_radeon_private_t *dev_priv = dev->dev_private;
2414 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2425 drm_radeon_private_t *dev_priv = dev->dev_private;
2464 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2465 VB_AGE_TEST_WITH_RETURN(dev_priv);
2494 drm_radeon_private_t *dev_priv = dev->dev_private;
2496 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2519 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2520 VB_AGE_TEST_WITH_RETURN(dev_priv);
2553 if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
2590 static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2611 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
2626 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2648 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2668 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2690 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2720 drm_radeon_private_t *dev_priv = dev->dev_private;
2727 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2747 drm_radeon_private_t *dev_priv = dev->dev_private;
2757 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2775 radeon_emit_clip_rect(dev_priv, &box);
2794 drm_radeon_private_t *dev_priv = dev->dev_private;
2824 drm_radeon_private_t *dev_priv = dev->dev_private;
2842 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2843 VB_AGE_TEST_WITH_RETURN(dev_priv);
2868 if (dev_priv->microcode_version == UCODE_R300) {
2889 (dev_priv, filp_priv, header, &cmdbuf)) {
2897 if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
2905 if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
2949 if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
2964 if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) {
2994 drm_radeon_private_t *dev_priv = dev->dev_private;
3005 value = dev_priv->gart_buffers_offset;
3008 dev_priv->stats.last_frame_reads++;
3015 dev_priv->stats.last_clear_reads++;
3022 value = dev_priv->gart_vm_start;
3025 value = dev_priv->mmio->offset;
3028 value = dev_priv->ring_rptr_offset;
3046 value = dev_priv->gart_textures_offset;
3049 if (!dev_priv->writeback_works)
3054 if (dev_priv->flags & RADEON_IS_PCIE)
3056 else if (dev_priv->flags & RADEON_IS_AGP)
3077 drm_radeon_private_t *dev_priv = dev->dev_private;
3090 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3095 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3096 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3097 dev_priv->sarea_priv->tiling_enabled = 0;
3100 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3101 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3102 dev_priv->sarea_priv->tiling_enabled = 1;
3106 dev_priv->pcigart_offset = sp.value;
3107 dev_priv->pcigart_offset_set = 1;
3110 dev_priv->new_memmap = sp.value;
3113 dev_priv->gart_info.table_size = sp.value;
3114 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3115 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3135 drm_radeon_private_t *dev_priv = dev->dev_private;
3136 dev_priv->page_flipping = 0;
3137 radeon_mem_release(filp, dev_priv->gart_heap);
3138 radeon_mem_release(filp, dev_priv->fb_heap);
3139 radeon_surfaces_release(filp, dev_priv);
3146 drm_radeon_private_t *dev_priv = dev->dev_private;
3148 if (dev_priv->sarea_priv &&
3149 dev_priv->sarea_priv->pfCurrentPage != 0)
3158 drm_radeon_private_t *dev_priv = dev->dev_private;
3171 if (dev_priv)
3172 radeon_priv->radeon_fb_delta = dev_priv->fb_location;