Lines Matching defs:lanai
0 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
164 #define DEV_LABEL "lanai"
307 static void vci_bitfield_iterate(struct lanai_dev *lanai,
313 func(lanai, vci);
339 if (bytes > (128 * 1024)) /* max lanai buffer size */
348 * everything, but the way the lanai uses DMA memory would
444 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
473 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
476 return lanai->base + reg;
479 static inline u32 reg_read(const struct lanai_dev *lanai,
483 t = readl(reg_addr(lanai, reg));
484 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
489 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
492 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
494 writel(val, reg_addr(lanai, reg));
497 static inline void conf1_write(const struct lanai_dev *lanai)
499 reg_write(lanai, lanai->conf1, Config1_Reg);
502 static inline void conf2_write(const struct lanai_dev *lanai)
504 reg_write(lanai, lanai->conf2, Config2_Reg);
508 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
511 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
514 conf2_write(lanai);
517 static inline void reset_board(const struct lanai_dev *lanai)
520 reg_write(lanai, 0, Reset_Reg);
540 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
542 return lanai->base + SRAM_START + offset;
545 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
547 return readl(sram_addr(lanai, offset));
550 static inline void sram_write(const struct lanai_dev *lanai,
553 writel(val, sram_addr(lanai, offset));
557 const struct lanai_dev *lanai, int offset, u32 pattern)
560 sram_write(lanai, pattern, offset);
561 readback = sram_read(lanai, offset);
566 lanai->number, offset,
571 static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
575 result = sram_test_word(lanai, offset, pattern);
579 static int __devinit sram_test_and_clear(const struct lanai_dev *lanai)
584 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
586 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
590 return sram_test_pass(lanai, 0x0000);
645 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
648 return sram_addr(lanai, vci * CARDVCC_SIZE);
770 * Unfortunately the lanai needs us to wait until all the data
776 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
790 __clear_bit(lvcc->vci, lanai->backlog_vccs);
832 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
835 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
836 lanai->pci);
837 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
840 static inline void aal0_buffer_free(struct lanai_dev *lanai)
843 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
865 static int __devinit eeprom_read(struct lanai_dev *lanai)
868 lanai->number);
869 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
873 static int __devinit eeprom_validate(struct lanai_dev *lanai)
875 lanai->serialno = 0;
876 lanai->magicno = EEPROM_MAGIC_VALUE;
882 static int __devinit eeprom_read(struct lanai_dev *lanai)
887 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
889 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
890 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
891 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
892 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
894 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
905 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
907 if (lanai->conf1 != tmp) {
930 lanai->eeprom[address] = data;
939 lanai->number, address);
952 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
954 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
958 static int __devinit eeprom_validate(struct lanai_dev *lanai)
962 const u8 *e = lanai->eeprom;
982 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
989 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
998 "(0x%02X, inverse 0x%02X)\n", lanai->number,
1007 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
1008 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
1009 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
1011 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1012 (unsigned int) lanai->serialno, (unsigned int) v);
1015 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1017 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1018 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1019 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1021 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1022 lanai->magicno, v);
1025 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1026 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1029 lanai->number, (unsigned int) lanai->magicno,
1036 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1038 return &lanai->eeprom[EEPROM_MAC];
1057 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1068 static inline u32 intr_pending(const struct lanai_dev *lanai)
1070 return reg_read(lanai, IntStatusMasked_Reg);
1073 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1075 reg_write(lanai, i, IntControlEna_Reg);
1078 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1080 reg_write(lanai, i, IntControlDis_Reg);
1092 static void lanai_check_status(struct lanai_dev *lanai)
1094 u32 new = reg_read(lanai, Status_Reg);
1095 u32 changes = new ^ lanai->status;
1096 lanai->status = new;
1099 status_message(lanai->number, name, new & flag)
1112 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1116 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1119 "%d\n", lanai->number, result);
1127 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1130 "%d\n", lanai->number, result);
1135 pcistatus_got(lanai->number, name); \
1136 ++lanai->stats.pcierr_##stat; \
1249 static inline void lanai_endtx(struct lanai_dev *lanai,
1265 spin_lock(&lanai->endtxlock);
1272 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1275 "always busy!\n", lanai->number);
1286 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1287 spin_unlock(&lanai->endtxlock);
1294 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1308 lanai_endtx(lanai, lvcc);
1314 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1333 lanai_send_one_aal5(lanai, lvcc, skb, n);
1338 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1343 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1354 __set_bit(lvcc->vci, lanai->backlog_vccs);
1359 lanai_send_one_aal5(lanai, lvcc, skb, n);
1362 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1369 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1439 static void vcc_rx_aal0(struct lanai_dev *lanai)
1455 static int __devinit vcc_table_allocate(struct lanai_dev *lanai)
1458 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1460 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1461 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1463 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1464 lanai->vccs = (struct lanai_vcc **) vmalloc(bytes);
1465 if (unlikely(lanai->vccs == NULL))
1467 memset(lanai->vccs, 0, bytes);
1472 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1475 free_page((unsigned long) lanai->vccs);
1477 vfree(lanai->vccs);
1495 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1504 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1509 "for %s buffer, got only %Zu\n", lanai->number, size,
1516 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1519 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1524 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1537 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1541 static inline void host_vcc_bind(struct lanai_dev *lanai,
1548 if (lanai->nbound++ == 0) {
1550 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1551 conf1_write(lanai);
1552 conf2_write(lanai);
1555 lvcc->vbase = cardvcc_addr(lanai, vci);
1556 lanai->vccs[lvcc->vci = vci] = lvcc;
1559 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1566 lanai->vccs[lvcc->vci] = NULL;
1568 if (--lanai->nbound == 0) {
1570 lanai->conf1 |= CONFIG1_POWERDOWN;
1571 conf1_write(lanai);
1578 static void lanai_reset(struct lanai_dev *lanai)
1581 "implemented\n", lanai->number);
1587 reg_write(lanai, INT_ALL, IntAck_Reg);
1588 lanai->stats.card_reset++;
1596 static int __devinit service_buffer_allocate(struct lanai_dev *lanai)
1598 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1599 lanai->pci);
1600 if (unlikely(lanai->service.start == NULL))
1603 (unsigned long) lanai->service.start,
1604 lanai_buf_size(&lanai->service),
1605 lanai_buf_size_cardorder(&lanai->service));
1607 reg_write(lanai, 0, ServWrite_Reg);
1609 reg_write(lanai,
1610 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1611 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1616 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1618 lanai_buf_deallocate(&lanai->service, lanai->pci);
1634 static int handle_service(struct lanai_dev *lanai, u32 s)
1639 lvcc = lanai->vccs[vci];
1643 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1645 lanai->stats.service_notx++;
1647 lanai->stats.service_norx++;
1654 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1655 lanai->stats.service_notx++;
1658 __set_bit(vci, lanai->transmit_ready);
1666 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1667 lanai->stats.service_norx++;
1673 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1674 lanai->stats.service_rxnotaal5++;
1694 lanai->stats.ovfl_trash += (bytes / 48);
1702 "PDU on VCI %d!\n", lanai->number, vci);
1703 lanai_reset(lanai);
1716 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1718 struct lanai_vcc *lvcc = lanai->vccs[vci];
1720 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1724 * interrupts otherwise disabled and with the lanai->servicelock
1727 static void run_service(struct lanai_dev *lanai)
1730 u32 wreg = reg_read(lanai, ServWrite_Reg);
1731 const u32 *end = lanai->service.start + wreg;
1732 while (lanai->service.ptr != end) {
1733 ntx += handle_service(lanai,
1734 le32_to_cpup(lanai->service.ptr++));
1735 if (lanai->service.ptr >= lanai->service.end)
1736 lanai->service.ptr = lanai->service.start;
1738 reg_write(lanai, wreg, ServRead_Reg);
1741 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1743 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1750 static void get_statistics(struct lanai_dev *lanai)
1752 u32 statreg = reg_read(lanai, Statistics_Reg);
1753 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1754 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1755 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1756 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1763 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1765 struct lanai_vcc *lvcc = lanai->vccs[vci];
1769 __clear_bit(vci, lanai->backlog_vccs);
1773 lvcc->tx.unqueue(lanai, lvcc, endptr);
1779 struct lanai_dev *lanai = (struct lanai_dev *) arg;
1783 if (lanai->conf1 & CONFIG1_POWERDOWN)
1788 if (spin_trylock(&lanai->servicelock)) {
1789 run_service(lanai);
1790 spin_unlock(&lanai->servicelock);
1795 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1799 get_statistics(lanai);
1801 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1804 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1806 init_timer(&lanai->timer);
1807 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1808 lanai->timer.data = (unsigned long) lanai;
1809 lanai->timer.function = lanai_timed_poll;
1810 add_timer(&lanai->timer);
1813 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1815 del_timer_sync(&lanai->timer);
1820 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1825 spin_lock(&lanai->servicelock);
1826 run_service(lanai);
1827 spin_unlock(&lanai->servicelock);
1831 vcc_rx_aal0(lanai);
1838 get_statistics(lanai);
1842 lanai_check_status(lanai);
1847 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1848 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1850 lanai_reset(lanai);
1855 lanai->number);
1856 conf1_write(lanai);
1857 lanai->stats.dma_reenable++;
1858 pcistatus_check(lanai, 0);
1863 lanai->number);
1864 pcistatus_check(lanai, 0);
1868 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1870 lanai_reset(lanai);
1876 lanai->number,
1878 lanai_reset(lanai);
1890 reg_write(lanai, ack, IntAck_Reg);
1895 struct lanai_dev *lanai = devid;
1904 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1908 reason = intr_pending(lanai);
1915 lanai_int_1(lanai, reason);
1916 reason = intr_pending(lanai);
1950 static int __devinit lanai_pci_start(struct lanai_dev *lanai)
1952 struct pci_dev *pci = lanai->pci;
1958 "PCI device", lanai->number);
1964 "(itf %d): No suitable DMA available.\n", lanai->number);
1969 "(itf %d): No suitable DMA available.\n", lanai->number);
1974 &lanai->pci_revision);
1977 "PCI_REVISION_ID: %d\n", lanai->number, result);
1983 "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result);
1989 /* Set latency timer to zero as per lanai docs */
1993 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1996 pcistatus_check(lanai, 1);
1997 pcistatus_check(lanai, 0);
2009 static inline int vci0_is_ok(struct lanai_dev *lanai,
2015 if (lanai->naal0 != 0)
2017 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
2018 conf2_write_if_powerup(lanai);
2026 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
2030 const struct lanai_vcc *lvcc = lanai->vccs[vci];
2031 if (vci == 0 && !vci0_is_ok(lanai, qos))
2041 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2044 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2046 const struct lanai_vcc *vci0 = lanai->vccs[0];
2049 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2050 conf2_write_if_powerup(lanai);
2055 static int lanai_normalize_ci(struct lanai_dev *lanai,
2069 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2071 if (vci_is_ok(lanai, *vcip, atmvcc))
2075 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2076 !vci_is_ok(lanai, *vcip, atmvcc))
2129 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2131 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2132 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2133 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2134 conf2_write(lanai);
2137 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2139 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2140 conf2_write(lanai);
2148 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2154 lanai->number = atmdev->number;
2155 lanai->num_vci = NUM_VCI;
2156 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2157 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2158 lanai->naal0 = 0;
2160 lanai->nbound = 0;
2162 lanai->cbrvcc = NULL;
2163 memset(&lanai->stats, 0, sizeof lanai->stats);
2164 spin_lock_init(&lanai->endtxlock);
2165 spin_lock_init(&lanai->servicelock);
2168 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2173 if ((result = lanai_pci_start(lanai)) != 0)
2175 raw_base = lanai->pci->resource[0].start;
2176 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2177 if (lanai->base == NULL) {
2181 /* 3.3: Reset lanai and PHY */
2182 reset_board(lanai);
2183 lanai->conf1 = reg_read(lanai, Config1_Reg);
2184 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2186 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2187 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2189 conf1_write(lanai);
2201 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2206 if ((result = eeprom_read(lanai)) != 0)
2208 if ((result = eeprom_validate(lanai)) != 0)
2212 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2214 conf1_write(lanai);
2216 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2217 conf1_write(lanai);
2220 if ((result = sram_test_and_clear(lanai)) != 0)
2223 /* 3.10: initialize lanai registers */
2224 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2225 conf1_write(lanai);
2226 if ((result = service_buffer_allocate(lanai)) != 0)
2228 if ((result = vcc_table_allocate(lanai)) != 0)
2230 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2232 conf2_write(lanai);
2233 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2234 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
2235 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2236 DEV_LABEL, lanai)) != 0) {
2241 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2243 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2246 conf1_write(lanai);
2247 lanai->status = reg_read(lanai, Status_Reg);
2250 lanai->conf1 |= CONFIG1_POWERDOWN;
2251 conf1_write(lanai);
2253 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2254 lanai_timed_poll_start(lanai);
2256 "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
2257 (int) lanai->pci_revision, (unsigned long) lanai->base,
2258 lanai->pci->irq,
2262 "board_rev=%d\n", lanai->number,
2263 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2264 (unsigned int) lanai->serialno, lanai->board_rev);
2268 vcc_table_deallocate(lanai);
2270 service_buffer_deallocate(lanai);
2272 reset_board(lanai);
2274 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2275 conf1_write(lanai);
2277 iounmap(lanai->base);
2279 pci_disable_device(lanai->pci);
2289 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2291 lanai->number);
2292 lanai_timed_poll_stop(lanai);
2294 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2295 conf1_write(lanai);
2297 intr_disable(lanai, INT_ALL);
2298 free_irq(lanai->pci->irq, lanai);
2299 reset_board(lanai);
2301 lanai->conf1 |= CONFIG1_POWERDOWN;
2302 conf1_write(lanai);
2304 pci_disable_device(lanai->pci);
2305 vcc_table_deallocate(lanai);
2306 service_buffer_deallocate(lanai);
2307 iounmap(lanai->base);
2308 kfree(lanai);
2315 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2323 if (--lanai->naal0 <= 0)
2324 aal0_buffer_free(lanai);
2326 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2330 if (atmvcc == lanai->cbrvcc) {
2332 lanai_cbr_shutdown(lanai);
2333 lanai->cbrvcc = NULL;
2335 lanai_shutdown_tx_vci(lanai, lvcc);
2336 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2340 host_vcc_unbind(lanai, lvcc);
2350 struct lanai_dev *lanai;
2359 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2360 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2366 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2368 lvcc = lanai->vccs[vci];
2380 if (lanai->naal0 == 0)
2381 result = aal0_buffer_allocate(lanai);
2384 lanai, lvcc, &atmvcc->qos);
2394 lanai->naal0++;
2399 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2404 APRINTK(lanai->cbrvcc == NULL,
2406 lanai->cbrvcc = atmvcc;
2409 host_vcc_bind(lanai, lvcc, vci);
2419 if (lanai->cbrvcc == atmvcc)
2420 lanai_cbr_setup(lanai);
2433 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2443 if (unlikely(lanai == NULL)) {
2444 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2452 vcc_tx_aal5(lanai, lvcc, skb);
2461 vcc_tx_aal0(lanai, lvcc, skb);
2483 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2489 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2490 (unsigned int) lanai->serialno,
2491 (unsigned int) lanai->magicno, lanai->num_vci);
2494 lanai->board_rev, (int) lanai->pci_revision);
2498 lanai->eeprom[EEPROM_MAC + 0],
2499 lanai->eeprom[EEPROM_MAC + 1],
2500 lanai->eeprom[EEPROM_MAC + 2],
2501 lanai->eeprom[EEPROM_MAC + 3],
2502 lanai->eeprom[EEPROM_MAC + 4],
2503 lanai->eeprom[EEPROM_MAC + 5]);
2506 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2507 (lanai->status & STATUS_LOCD) ? 1 : 0,
2508 (lanai->status & STATUS_LED) ? 1 : 0,
2509 (lanai->status & STATUS_GPIN) ? 1 : 0);
2512 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2513 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2515 get_statistics(lanai);
2518 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2519 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2524 lanai->stats.pcierr_parity_detect,
2525 lanai->stats.pcierr_serr_set,
2526 lanai->stats.pcierr_m_target_abort);
2529 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2530 lanai->stats.pcierr_master_parity);
2533 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2534 lanai->stats.service_notx,
2535 lanai->stats.service_rxnotaal5);
2538 lanai->stats.dma_reenable, lanai->stats.card_reset);
2546 if ((lvcc = lanai->vccs[left]) != NULL)
2571 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2601 struct lanai_dev *lanai;
2605 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
2606 if (lanai == NULL) {
2616 kfree(lanai);
2620 atmdev->dev_data = lanai;
2621 lanai->pci = pci;
2622 lanai->type = (enum lanai_type) ident->device;
2628 kfree(lanai);