Lines Matching refs:psgl
60 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
68 if (psgl->dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
69 printk("ppc4xx_add_dma_sgl: bad channel: %d\n", psgl->dmanr);
73 p_dma_ch = &dma_channels[psgl->dmanr];
108 if ((unsigned) (psgl->ptail + 1) >= ((unsigned) psgl + SGL_LIST_SIZE)) {
113 if (!psgl->ptail) {
114 psgl->phead = (ppc_sgl_t *)
115 ((unsigned) psgl + sizeof (sgl_list_info_t));
116 psgl->phead_dma = psgl->dma_addr + sizeof(sgl_list_info_t);
117 psgl->ptail = psgl->phead;
118 psgl->ptail_dma = psgl->phead_dma;
123 psgl->ptail->control_count &=
126 psgl->ptail->next = psgl->ptail_dma + sizeof(ppc_sgl_t);
127 psgl->ptail++;
128 psgl->ptail_dma += sizeof(ppc_sgl_t);
131 psgl->ptail->control = psgl->control;
132 psgl->ptail->src_addr = src_addr;
133 psgl->ptail->dst_addr = dst_addr;
134 psgl->ptail->control_count = (count >> p_dma_ch->shift) |
135 psgl->sgl_control;
136 psgl->ptail->next = (uint32_t) NULL;
147 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
154 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
156 psgl->dmanr);
158 } else if (!psgl->phead) {
163 p_dma_ch = &dma_channels[psgl->dmanr];
164 psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */
167 ppc4xx_set_sg_addr(psgl->dmanr, psgl->phead_dma);
169 sg_command |= SSG_ENABLE(psgl->dmanr);
180 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
186 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
188 psgl->dmanr);
193 sg_command &= ~SSG_ENABLE(psgl->dmanr);
208 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
216 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
218 psgl->dmanr);
222 sgl_addr = (ppc_sgl_t *) __va(mfdcr(DCRN_ASG0 + (psgl->dmanr * 0x8)));
223 count_left = mfdcr(DCRN_DMACT0 + (psgl->dmanr * 0x8)) & SG_COUNT_MASK;
230 pnext = psgl->phead;
232 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) &&
250 while ((pnext != psgl->ptail) &&
251 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE))
256 if (pnext != psgl->ptail) { /* should never happen */
258 ("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n",
259 (unsigned int) psgl->ptail, (unsigned int) handle);
264 p_dma_ch = &dma_channels[psgl->dmanr];
292 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
297 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
299 psgl->dmanr);
303 if (!psgl->phead) {
310 *src_dma_addr = (phys_addr_t) psgl->phead->src_addr;
311 *dst_dma_addr = (phys_addr_t) psgl->phead->dst_addr;
313 if (psgl->phead == psgl->ptail) {
315 psgl->phead = NULL;
316 psgl->ptail = NULL;
318 psgl->phead++;
319 psgl->phead_dma += sizeof(ppc_sgl_t);
357 sgl_list_info_t *psgl=NULL;
378 psgl = (sgl_list_info_t *) ret;
381 if (psgl == NULL) {
386 psgl->dma_addr = dma_addr;
387 psgl->dmanr = dmanr;
395 psgl->control = p_dma_ch->control;
397 psgl->control &= ~(DMA_TM_MASK | DMA_TD);
399 psgl->control |= (mode | DMA_CE_ENABLE);
403 psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
407 psgl->control |= DMA_CIE_ENABLE;
409 psgl->control &= ~DMA_CIE_ENABLE;
417 psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
422 psgl->sgl_control |= ctc_settings;
426 psgl->sgl_control |= SG_TCI_ENABLE;
428 psgl->sgl_control |= SG_ETI_ENABLE;
431 *phandle = (sgl_handle_t) psgl;
442 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
447 } else if (psgl->phead) {
450 } else if (!psgl->dma_addr) { /* should never happen */
455 dma_free_coherent(NULL, DMA_PPC4xx_SIZE, (void *) psgl, 0);