Lines Matching refs:UIC0
91 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
92 #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
93 #define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
101 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
114 /* Enable cascade interrupts in UIC0 */
116 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
117 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
132 return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0)));
157 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
163 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
172 /* Enable cascade interrupt in UIC0 */
174 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
175 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
184 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
197 { .decl = DECLARE_UIC(0), .base = UIC0 },