Lines Matching refs:mpic
2 * arch/powerpc/kernel/mpic.c
36 #include <asm/mpic.h>
39 #include "mpic.h"
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
188 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
190 enum mpic_reg_type type = mpic->reg_type;
194 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
196 return _mpic_read(type, &mpic->gregs, offset);
199 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
204 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
207 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
211 if (mpic->flags & MPIC_PRIMARY)
213 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
216 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
220 if (mpic->flags & MPIC_PRIMARY)
223 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
226 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
228 unsigned int isu = src_no >> mpic->isu_shift;
229 unsigned int idx = src_no & mpic->isu_mask;
231 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
235 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
238 unsigned int isu = src_no >> mpic->isu_shift;
239 unsigned int idx = src_no & mpic->isu_mask;
241 _mpic_write(mpic->reg_type, &mpic->isus[isu],
245 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
246 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
247 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
248 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
249 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
250 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
251 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
252 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
260 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
269 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
272 rb->dbase = mpic->dcr_base;
274 rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size);
278 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
282 if (mpic->flags & MPIC_USES_DCR)
283 _mpic_map_dcr(mpic, rb, offset, size);
285 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
296 static void __init mpic_test_broken_ipi(struct mpic *mpic)
300 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
301 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
304 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
305 mpic->flags |= MPIC_BROKEN_IPI;
311 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
313 if (source >= 128 || !mpic->fixups)
315 return mpic->fixups[source].base != NULL;
319 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
321 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
328 spin_lock(&mpic->fixup_lock);
331 spin_unlock(&mpic->fixup_lock);
335 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
338 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
347 spin_lock_irqsave(&mpic->fixup_lock, flags);
355 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
360 mpic->save_data[source].fixup_data = tmp | 1;
364 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
367 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
377 spin_lock_irqsave(&mpic->fixup_lock, flags);
382 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
387 mpic->save_data[source].fixup_data = tmp & ~1;
392 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
420 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
428 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
435 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
459 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
471 mpic->fixups[irq].index = i;
472 mpic->fixups[irq].base = base;
475 mpic->fixups[irq].applebase = devbase + 0x60;
477 mpic->fixups[irq].applebase = NULL;
479 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
484 static void __init mpic_scan_ht_pics(struct mpic *mpic)
489 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
492 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
493 BUG_ON(mpic->fixups == NULL);
494 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
497 spin_lock_init(&mpic->fixup_lock);
525 mpic_scan_ht_pic(mpic, devbase, devfn, l);
526 mpic_scan_ht_msi(mpic, devbase, devfn);
537 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
542 static void __init mpic_scan_ht_pics(struct mpic *mpic)
551 /* Find an mpic associated with a given linux interrupt */
552 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
555 struct mpic *mpic;
560 mpic = irq_desc[irq].chip_data;
563 *is_ipi = (src >= mpic->ipi_vecs[0] &&
564 src <= mpic->ipi_vecs[3]);
566 return mpic;
581 /* Get the mpic structure from the IPI number */
582 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
588 /* Get the mpic structure from the irq number */
589 static inline struct mpic * mpic_from_irq(unsigned int irq)
595 static inline void mpic_eoi(struct mpic *mpic)
604 struct mpic *mpic;
606 mpic = mpic_find(irq, NULL);
607 smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]);
621 struct mpic *mpic = mpic_from_irq(irq);
624 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
641 struct mpic *mpic = mpic_from_irq(irq);
644 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
661 struct mpic *mpic = mpic_from_irq(irq);
664 DBG("%s: end_irq: %d\n", mpic->name, irq);
671 mpic_eoi(mpic);
678 struct mpic *mpic = mpic_from_irq(irq);
684 mpic_ht_end_irq(mpic, src);
689 struct mpic *mpic = mpic_from_irq(irq);
693 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
700 struct mpic *mpic = mpic_from_irq(irq);
703 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
709 struct mpic *mpic = mpic_from_irq(irq);
713 DBG("%s: end_irq: %d\n", mpic->name, irq);
721 mpic_ht_end_irq(mpic, src);
722 mpic_eoi(mpic);
730 struct mpic *mpic = mpic_from_ipi(irq);
731 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
733 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
744 struct mpic *mpic = mpic_from_ipi(irq);
753 mpic_eoi(mpic);
760 struct mpic *mpic = mpic_from_irq(irq);
771 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
794 struct mpic *mpic = mpic_from_irq(virq);
799 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
800 mpic, virq, src, flow_type);
802 if (src >= mpic->irq_count)
806 if (mpic->senses && src < mpic->senses_count)
807 flow_type = mpic->senses[src];
816 if (mpic_is_ht_interrupt(mpic, src))
820 vecpri = mpic_type_to_vecpri(mpic, flow_type);
861 struct mpic *mpic = h->host_data;
863 /* Exact match, unless mpic node is NULL */
864 return mpic->of_node == NULL || mpic->of_node == node;
870 struct mpic *mpic = h->host_data;
873 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
875 if (hw == mpic->spurious_vec)
879 else if (hw >= mpic->ipi_vecs[0]) {
880 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
882 DBG("mpic: mapping as IPI\n");
883 set_irq_chip_data(virq, mpic);
884 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
890 if (hw >= mpic->irq_count)
893 mpic_msi_reserve_hwirq(mpic, hw);
896 chip = &mpic->hc_irq;
900 if (mpic_is_ht_interrupt(mpic, hw))
901 chip = &mpic->hc_ht_irq;
904 DBG("mpic: mapping to irq chip @%p\n", chip);
906 set_irq_chip_data(virq, mpic);
947 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
963 struct mpic * __init mpic_alloc(struct device_node *node,
970 struct mpic *mpic;
977 mpic = alloc_bootmem(sizeof(struct mpic));
978 if (mpic == NULL)
981 memset(mpic, 0, sizeof(struct mpic));
982 mpic->name = name;
983 mpic->of_node = of_node_get(node);
985 mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size,
988 if (mpic->irqhost == NULL) {
993 mpic->irqhost->host_data = mpic;
994 mpic->hc_irq = mpic_irq_chip;
995 mpic->hc_irq.typename = name;
997 mpic->hc_irq.set_affinity = mpic_set_affinity;
999 mpic->hc_ht_irq = mpic_irq_ht_chip;
1000 mpic->hc_ht_irq.typename = name;
1002 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1006 mpic->hc_ipi = mpic_ipi_chip;
1007 mpic->hc_ipi.typename = name;
1010 mpic->flags = flags;
1011 mpic->isu_size = isu_size;
1012 mpic->irq_count = irq_count;
1013 mpic->num_sources = 0; /* so far */
1020 mpic->timer_vecs[0] = intvec_top - 8;
1021 mpic->timer_vecs[1] = intvec_top - 7;
1022 mpic->timer_vecs[2] = intvec_top - 6;
1023 mpic->timer_vecs[3] = intvec_top - 5;
1024 mpic->ipi_vecs[0] = intvec_top - 4;
1025 mpic->ipi_vecs[1] = intvec_top - 3;
1026 mpic->ipi_vecs[2] = intvec_top - 2;
1027 mpic->ipi_vecs[3] = intvec_top - 1;
1028 mpic->spurious_vec = intvec_top;
1032 mpic->flags |= MPIC_BIG_ENDIAN;
1036 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1040 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1048 mpic->flags |= MPIC_USES_DCR;
1051 if (mpic->flags & MPIC_USES_DCR) {
1055 mpic->dcr_base = *dbasep;
1056 mpic->reg_type = mpic_access_dcr;
1059 BUG_ON (mpic->flags & MPIC_USES_DCR);
1065 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1074 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1075 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1079 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1080 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1082 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1091 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1092 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1095 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1099 for (i = 0; i < mpic->num_cpus; i++) {
1100 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1106 if (mpic->isu_size == 0) {
1107 mpic->isu_size = mpic->num_sources;
1108 mpic_map(mpic, paddr, &mpic->isus[0],
1109 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1111 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1112 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1129 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1131 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1132 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1133 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1135 mpic->next = mpics;
1136 mpics = mpic;
1139 mpic_primary = mpic;
1140 irq_set_default_host(mpic->irqhost);
1143 return mpic;
1146 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1149 unsigned int isu_first = isu_num * mpic->isu_size;
1153 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1154 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1155 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1156 mpic->num_sources = isu_first + mpic->isu_size;
1159 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1161 mpic->senses = senses;
1162 mpic->senses_count = count;
1165 void __init mpic_init(struct mpic *mpic)
1169 BUG_ON(mpic->num_sources == 0);
1171 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1178 mpic_write(mpic->tmregs,
1181 mpic_write(mpic->tmregs,
1185 (mpic->timer_vecs[0] + i));
1189 mpic_test_broken_ipi(mpic);
1194 (mpic->ipi_vecs[0] + i));
1198 if (mpic->irq_count == 0)
1199 mpic->irq_count = mpic->num_sources;
1201 /* Do the HT PIC fixups on U3 broken mpic */
1202 DBG("MPIC flags: %x\n", mpic->flags);
1203 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1204 mpic_scan_ht_pics(mpic);
1205 mpic_u3msi_init(mpic);
1208 for (i = 0; i < mpic->num_sources; i++) {
1220 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1223 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1224 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1225 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1232 /* allocate memory to save mpic state */
1233 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1234 BUG_ON(mpic->save_data == NULL);
1238 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1242 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1245 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1248 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1254 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1259 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1266 struct mpic *mpic = mpic_find(irq, &is_ipi);
1273 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1275 mpic_ipi_write(src - mpic->ipi_vecs[0],
1289 struct mpic *mpic = mpic_find(irq, &is_ipi);
1296 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1306 struct mpic *mpic = mpic_primary;
1311 BUG_ON(mpic == NULL);
1313 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1317 /* let the mpic know we want intrs. default affinity is 0xffffffff
1323 for (i = 0; i < mpic->num_sources ; i++)
1337 struct mpic *mpic = mpic_primary;
1344 struct mpic *mpic = mpic_primary;
1352 struct mpic *mpic = mpic_primary;
1357 BUG_ON(mpic == NULL);
1359 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1362 /* let the mpic know we don't want intrs. */
1363 for (i = 0; i < mpic->num_sources ; i++)
1376 struct mpic *mpic = mpic_primary;
1378 BUG_ON(mpic == NULL);
1381 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1389 unsigned int mpic_get_one_irq(struct mpic *mpic)
1395 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1397 if (unlikely(src == mpic->spurious_vec)) {
1398 if (mpic->flags & MPIC_SPV_EOI)
1399 mpic_eoi(mpic);
1402 return irq_linear_revmap(mpic->irqhost, src);
1407 struct mpic *mpic = mpic_primary;
1409 BUG_ON(mpic == NULL);
1411 return mpic_get_one_irq(mpic);
1418 struct mpic *mpic = mpic_primary;
1426 BUG_ON(mpic == NULL);
1428 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1431 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1432 mpic->ipi_vecs[0] + i);
1439 ipi_names[i], mpic);
1494 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1497 for (i = 0; i < mpic->num_sources; i++) {
1498 mpic->save_data[i].vecprio =
1500 mpic->save_data[i].dest =
1509 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1512 for (i = 0; i < mpic->num_sources; i++) {
1514 mpic->save_data[i].vecprio);
1516 mpic->save_data[i].dest);
1520 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1524 if ((mpic->save_data[i].fixup_data & 1) == 0)
1530 writel(mpic->save_data[i].fixup_data & ~1,
1546 set_kset_name("mpic"),
1551 struct mpic *mpic = mpics;
1556 while (mpic && !error) {
1557 mpic->sysdev.cls = &mpic_sysclass;
1558 mpic->sysdev.id = id++;
1559 error = sysdev_register(&mpic->sysdev);
1560 mpic = mpic->next;