Lines Matching defs:priv2
161 struct spu_priv2 __iomem *priv2 = spu->priv2;
166 switch (in_be64(&priv2->mfc_control_RW) &
169 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
175 csa->priv2.mfc_control_RW =
176 in_be64(&priv2->mfc_control_RW) |
181 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
182 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
186 csa->priv2.mfc_control_RW =
187 in_be64(&priv2->mfc_control_RW) &
241 struct spu_priv2 __iomem *priv2 = spu->priv2;
247 if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
248 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
250 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
252 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
255 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
261 struct spu_priv2 __iomem *priv2 = spu->priv2;
267 out_be64(&priv2->mfc_control_RW, MFC_CNTL_DECREMENTER_HALTED);
330 struct spu_priv2 __iomem *priv2 = spu->priv2;
337 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
339 csa->priv2.puq[i].mfc_cq_data0_RW =
340 in_be64(&priv2->puq[i].mfc_cq_data0_RW);
341 csa->priv2.puq[i].mfc_cq_data1_RW =
342 in_be64(&priv2->puq[i].mfc_cq_data1_RW);
343 csa->priv2.puq[i].mfc_cq_data2_RW =
344 in_be64(&priv2->puq[i].mfc_cq_data2_RW);
345 csa->priv2.puq[i].mfc_cq_data3_RW =
346 in_be64(&priv2->puq[i].mfc_cq_data3_RW);
349 csa->priv2.spuq[i].mfc_cq_data0_RW =
350 in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
351 csa->priv2.spuq[i].mfc_cq_data1_RW =
352 in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
353 csa->priv2.spuq[i].mfc_cq_data2_RW =
354 in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
355 csa->priv2.spuq[i].mfc_cq_data3_RW =
356 in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
385 struct spu_priv2 __iomem *priv2 = spu->priv2;
391 csa->priv2.spu_tag_status_query_RW =
392 in_be64(&priv2->spu_tag_status_query_RW);
397 struct spu_priv2 __iomem *priv2 = spu->priv2;
403 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
404 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
409 struct spu_priv2 __iomem *priv2 = spu->priv2;
415 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
440 struct spu_priv2 __iomem *priv2 = spu->priv2;
446 out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
452 struct spu_priv2 __iomem *priv2 = spu->priv2;
458 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
493 struct spu_priv2 __iomem *priv2 = spu->priv2;
498 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
503 struct spu_priv2 __iomem *priv2 = spu->priv2;
509 out_be64(&priv2->spu_privcntl_RW, 0UL);
515 struct spu_priv2 __iomem *priv2 = spu->priv2;
520 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
525 struct spu_priv2 __iomem *priv2 = spu->priv2;
531 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
537 struct spu_priv2 __iomem *priv2 = spu->priv2;
542 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
587 struct spu_priv2 __iomem *priv2 = spu->priv2;
592 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
597 struct spu_priv2 __iomem *priv2 = spu->priv2;
605 out_be64(&priv2->spu_chnlcntptr_RW, 1);
606 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
611 out_be64(&priv2->spu_chnlcntptr_RW, idx);
613 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
614 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
615 out_be64(&priv2->spu_chnldata_RW, 0UL);
616 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
623 struct spu_priv2 __iomem *priv2 = spu->priv2;
629 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
631 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
633 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
635 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
641 struct spu_priv2 __iomem *priv2 = spu->priv2;
646 out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
648 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
654 struct spu_priv2 __iomem *priv2 = spu->priv2;
665 out_be64(&priv2->spu_chnlcntptr_RW, idx);
667 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
674 struct spu_priv2 __iomem *priv2 = spu->priv2;
680 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
698 struct spu_priv2 __iomem *priv2 = spu->priv2;
700 out_be64(&priv2->slb_index_W, slbe);
702 out_be64(&priv2->slb_vsid_RW, slb[0]);
703 out_be64(&priv2->slb_esid_RW, slb[1]);
968 struct spu_priv2 __iomem *priv2 = spu->priv2;
975 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
983 struct spu_priv2 __iomem *priv2 = spu->priv2;
989 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1072 struct spu_priv2 __iomem *priv2 = spu->priv2;
1081 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1082 out_be64(&priv2->spu_chnldata_RW, 0UL);
1087 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1089 out_be64(&priv2->spu_chnldata_RW, 0UL);
1090 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1097 struct spu_priv2 __iomem *priv2 = spu->priv2;
1108 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1110 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1268 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1289 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1309 struct spu_priv2 __iomem *priv2 = spu->priv2;
1314 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1403 struct spu_priv2 __iomem *priv2 = spu->priv2;
1410 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1412 out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1413 csa->priv2.puq[i].mfc_cq_data0_RW);
1414 out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1415 csa->priv2.puq[i].mfc_cq_data1_RW);
1416 out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1417 csa->priv2.puq[i].mfc_cq_data2_RW);
1418 out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1419 csa->priv2.puq[i].mfc_cq_data3_RW);
1422 out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1423 csa->priv2.spuq[i].mfc_cq_data0_RW);
1424 out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1425 csa->priv2.spuq[i].mfc_cq_data1_RW);
1426 out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1427 csa->priv2.spuq[i].mfc_cq_data2_RW);
1428 out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1429 csa->priv2.spuq[i].mfc_cq_data3_RW);
1459 struct spu_priv2 __iomem *priv2 = spu->priv2;
1464 out_be64(&priv2->spu_tag_status_query_RW,
1465 csa->priv2.spu_tag_status_query_RW);
1471 struct spu_priv2 __iomem *priv2 = spu->priv2;
1477 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1478 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1484 struct spu_priv2 __iomem *priv2 = spu->priv2;
1489 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1544 struct spu_priv2 __iomem *priv2 = spu->priv2;
1552 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1553 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1558 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1560 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1561 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1568 struct spu_priv2 __iomem *priv2 = spu->priv2;
1582 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1584 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1591 struct spu_priv2 __iomem *priv2 = spu->priv2;
1596 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1602 struct spu_priv2 __iomem *priv2 = spu->priv2;
1607 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1632 struct spu_priv2 __iomem *priv2 = spu->priv2;
1638 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1640 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1642 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1664 struct spu_priv2 __iomem *priv2 = spu->priv2;
1672 dummy = in_be64(&priv2->puint_mb_R);
1712 struct spu_priv2 __iomem *priv2 = spu->priv2;
1717 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1719 if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1720 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1853 struct spu_priv2 __iomem *priv2 = spu->priv2;
1865 out_be64(&priv2->spu_privcntl_RW, 4LL);
1873 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
2162 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2163 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |