Lines Matching refs:irq_desc
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
204 irq_desc[PLD_IRQ_CF0 + i].action = 0;
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */