Lines Matching refs:irq_desc
303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type;
305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type;
314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1;
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type;
322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type;
330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type;
338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type;
346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type;
354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1;
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type;
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type;
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
379 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type;
380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type;
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type;
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
418 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
419 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type;
420 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
437 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type;
438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1;