Lines Matching refs:r1
165 unsigned long r1:7; /* [6:12] */
179 UPD_IMMEDIATE, /* ldXZ r1=[r3],imm(9) */
180 UPD_REG /* ldXZ r1=[r3],r2 */
210 RPT(r1), RPT(r2), RPT(r3),
303 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)
313 long ridx = r1 - 32;
317 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
325 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
345 DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
376 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)
386 long ridx = r1 - 32;
390 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
398 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
416 DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);
691 * Load +Imm: ldXZ r1=[r3],imm(9)
718 * Load +Reg Opcode: ldXZ r1=[r3],r2
773 setreg(ld.r1, val, 0, regs);
799 * - suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the
806 * clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now
808 * If we look at the store, basically a stX [r3]=r1 checks the ALAT for any entry
813 * ld4.a r1=[r3]
816 * ld1.a r1=[r3],1
818 * ld1.a r1=[r3],1
820 * ld1.a r1=[r3],1
822 * ld1.a r1=[r3]
824 * r1=temporary
826 * So in this case, you would get the right value is r1 but the wrong info in
863 invala_gr(ld.r1);
914 imm = ld.x << 7 | ld.r1;
1051 DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);
1072 setfpreg(ld.r1, &fpr_final[0], regs);
1104 invala_fr(ld.r1);
1141 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1161 setfpreg(ld.r1, &fpr_final, regs);
1174 invala_fr(ld.r1);
1219 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1239 imm = ld.x << 7 | ld.r1;
1374 DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "
1375 "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,