Lines Matching refs:p0
97 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16);
99 R1 = [p0];
108 [p0] = R0;
115 p0.l = (DMEM_CONTROL & 0xFFFF);
116 p0.h = (DMEM_CONTROL >> 16);
117 R1 = [p0];
126 [p0] = R0;
134 p0.h = hi(UART_LCR);
135 p0.l = lo(UART_LCR);
137 w[p0] = r0.L; /* To enable DLL writes */
140 p0.h = hi(UART_DLL);
141 p0.l = lo(UART_DLL);
143 w[p0] = r0.L;
146 p0.h = hi(UART_DLH);
147 p0.l = lo(UART_DLH);
149 w[p0] = r0.L;
152 p0.h = hi(UART_GCTL);
153 p0.l = lo(UART_GCTL);
155 w[p0] = r0.L; /* To enable UART clock */
199 p0.l = lo(EVT15);
200 p0.h = hi(EVT15);
203 [p0] = p1;
206 p0.l = lo(IMASK);
207 p0.h = hi(IMASK);
210 [p0] = p1;
214 p0.l = .LWAIT_HERE;
215 p0.h = .LWAIT_HERE;
216 reti = p0;
228 p0.l = lo(WDOGA_CTL);
229 p0.h = hi(WDOGA_CTL);
231 w[p0] = r0; /* watchdog off for now */
301 p0.h = hi(SICA_IWR0);
302 p0.l = lo(SICA_IWR0);
304 [p0] = r0;
320 p0.h = hi(PLL_LOCKCNT);
321 p0.l = lo(PLL_LOCKCNT);
323 w[p0] = r0.l;
341 p0.h = hi(PLL_CTL);
342 p0.l = lo(PLL_CTL); /* Load the address */
345 w[p0] = r0.l; /* Set the value */
350 p0.h = hi(PLL_STAT);
351 p0.l = lo(PLL_STAT);
358 p0.h = hi(PLL_DIV);
359 p0.l = lo(PLL_DIV);
360 w[p0] = r0.l;
363 p0.l = lo(EBIU_SDRRC);
364 p0.h = hi(EBIU_SDRRC);
366 w[p0] = r0.l;
369 p0.l = (EBIU_SDBCTL & 0xFFFF);
370 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
372 w[p0] = r0.l;
379 p0.h = hi(EBIU_SDSTAT);
380 p0.l = lo(EBIU_SDSTAT);
381 r2.l = w[p0];
407 p0.h = hi(FIO_INEN);
408 p0.l = lo(FIO_INEN);
410 w[p0] = r0.l;
412 p0.h = hi(FIO_DIR);
413 p0.l = lo(FIO_DIR);
415 w[p0] = r0.l;
417 p0.h = hi(FIO_FLAG_C);
418 p0.l = lo(FIO_FLAG_C);
420 w[p0] = r0.l;
424 p0.h = hi(IMASK);
425 p0.l = lo(IMASK);
427 [p0] = r0;
430 p0.h = hi(ILAT);
431 p0.l = lo(ILAT);
432 r0 = [p0];
433 [p0] = r0;