Lines Matching refs:p0
97 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16);
99 R1 = [p0];
108 [p0] = R0;
115 p0.l = (DMEM_CONTROL & 0xFFFF);
116 p0.h = (DMEM_CONTROL >> 16);
117 R1 = [p0];
126 [p0] = R0;
136 p0.h = hi(BFIN_PORT_MUX);
137 p0.l = lo(BFIN_PORT_MUX);
150 p0.h = hi(PORTF_FER);
151 p0.l = lo(PORTF_FER);
166 p0.h = hi(EMAC_SYSTAT);
167 p0.l = lo(EMAC_SYSTAT);
175 p0.h = hi(PORTH_FER);
176 p0.l = lo(PORTH_FER);
188 p0.h = hi(UART_LCR);
189 p0.l = lo(UART_LCR);
191 w[p0] = r0.L; /* To enable DLL writes */
194 p0.h = hi(UART_DLL);
195 p0.l = lo(UART_DLL);
197 w[p0] = r0.L;
200 p0.h = hi(UART_DLH);
201 p0.l = lo(UART_DLH);
203 w[p0] = r0.L;
206 p0.h = hi(UART_GCTL);
207 p0.l = lo(UART_GCTL);
209 w[p0] = r0.L; /* To enable UART clock */
253 p0.l = lo(EVT15);
254 p0.h = hi(EVT15);
257 [p0] = p1;
260 p0.l = lo(IMASK);
261 p0.h = hi(IMASK);
264 [p0] = p1;
268 p0.l = .LWAIT_HERE;
269 p0.h = .LWAIT_HERE;
270 reti = p0;
282 p0.l = lo(WDOG_CTL);
283 p0.h = hi(WDOG_CTL);
285 w[p0] = r0; /* watchdog off for now */
357 p0.h = hi(VR_CTL);
358 p0.l = lo(VR_CTL);
359 r0.l = w[p0];
361 w[p0] = r0.l;
364 p0.h = hi(SIC_IWR);
365 p0.l = lo(SIC_IWR);
368 [p0] = r0;
384 p0.h = hi(PLL_LOCKCNT);
385 p0.l = lo(PLL_LOCKCNT);
387 w[p0] = r0.l;
405 p0.h = hi(PLL_CTL);
406 p0.l = lo(PLL_CTL); /* Load the address */
409 w[p0] = r0.l; /* Set the value */
414 p0.h = hi(PLL_STAT);
415 p0.l = lo(PLL_STAT);
422 p0.h = hi(PLL_DIV);
423 p0.l = lo(PLL_DIV);
424 w[p0] = r0.l;
427 p0.l = lo(EBIU_SDRRC);
428 p0.h = hi(EBIU_SDRRC);
430 w[p0] = r0.l;
433 p0.l = (EBIU_SDBCTL & 0xFFFF);
434 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
436 w[p0] = r0.l;
443 p0.h = hi(EBIU_SDSTAT);
444 p0.l = lo(EBIU_SDSTAT);
445 r2.l = w[p0];
461 p0.h = hi(SIC_IWR);
462 p0.l = lo(SIC_IWR);
465 [p0] = r0;
482 p0.h = hi(PORTF_FER);
483 p0.l = lo(PORTF_FER);
485 w[p0] = r0.l;
489 p0.h = hi(PORTFIO);
490 p0.l = lo(PORTFIO);
492 w[p0] = r0.l;
503 p0 = r0;
504 lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
514 p0.h = hi(IMASK);
515 p0.l = lo(IMASK);
517 [p0] = r0;
520 p0.h = hi(ILAT);
521 p0.l = lo(ILAT);
522 r0 = [p0];
523 [p0] = r0;