Lines Matching refs:p0
129 p0.h = hi(FIO_MASKA_C);
130 p0.l = lo(FIO_MASKA_C);
132 w[p0] = r0.L; /* Disable all interrupts */
135 p0.h = hi(FIO_MASKB_C);
136 p0.l = lo(FIO_MASKB_C);
138 w[p0] = r0.L; /* Disable all interrupts */
142 p0.l = (IMEM_CONTROL & 0xFFFF);
143 p0.h = (IMEM_CONTROL >> 16);
144 R1 = [p0];
153 [p0] = R0;
160 p0.l = (DMEM_CONTROL & 0xFFFF);
161 p0.h = (DMEM_CONTROL >> 16);
162 R1 = [p0];
171 [p0] = R0;
179 p0.h = hi(UART_LCR);
180 p0.l = lo(UART_LCR);
182 w[p0] = r0.L; /* To enable DLL writes */
185 p0.h = hi(UART_DLL);
186 p0.l = lo(UART_DLL);
188 w[p0] = r0.L;
191 p0.h = hi(UART_DLH);
192 p0.l = lo(UART_DLH);
194 w[p0] = r0.L;
197 p0.h = hi(UART_GCTL);
198 p0.l = lo(UART_GCTL);
200 w[p0] = r0.L; /* To enable UART clock */
244 p0.l = lo(EVT15);
245 p0.h = hi(EVT15);
248 [p0] = p1;
251 p0.l = lo(IMASK);
252 p0.h = hi(IMASK);
255 [p0] = p1;
259 p0.l = .LWAIT_HERE;
260 p0.h = .LWAIT_HERE;
261 reti = p0;
273 p0.l = lo(WDOG_CTL);
274 p0.h = hi(WDOG_CTL);
276 w[p0] = r0; /* watchdog off for now */
346 p0.h = hi(SIC_IWR);
347 p0.l = lo(SIC_IWR);
350 [p0] = r0;
366 p0.h = hi(PLL_LOCKCNT);
367 p0.l = lo(PLL_LOCKCNT);
369 w[p0] = r0.l;
387 p0.h = hi(PLL_CTL);
388 p0.l = lo(PLL_CTL); /* Load the address */
391 w[p0] = r0.l; /* Set the value */
396 p0.h = hi(PLL_STAT);
397 p0.l = lo(PLL_STAT);
404 p0.h = hi(PLL_DIV);
405 p0.l = lo(PLL_DIV);
406 w[p0] = r0.l;
409 p0.l = lo(EBIU_SDRRC);
410 p0.h = hi(EBIU_SDRRC);
412 w[p0] = r0.l;
415 p0.l = (EBIU_SDBCTL & 0xFFFF);
416 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
418 w[p0] = r0.l;
425 p0.h = hi(EBIU_SDSTAT);
426 p0.l = lo(EBIU_SDSTAT);
427 r2.l = w[p0];
443 p0.h = hi(SIC_IWR);
444 p0.l = lo(SIC_IWR);
447 [p0] = r0;
460 p0.h = hi(FIO_INEN);
461 p0.l = lo(FIO_INEN);
463 w[p0] = r0.l;
465 p0.h = hi(FIO_DIR);
466 p0.l = lo(FIO_DIR);
468 w[p0] = r0.l;
470 p0.h = hi(FIO_FLAG_C);
471 p0.l = lo(FIO_FLAG_C);
473 w[p0] = r0.l;
477 p0.h = hi(IMASK);
478 p0.l = lo(IMASK);
480 [p0] = r0;
483 p0.h = hi(ILAT);
484 p0.l = lo(ILAT);
485 r0 = [p0];
486 [p0] = r0;
530 p0.h = hi(PLL_CTL);
531 p0.l = lo(PLL_CTL); /* Load the address */
534 w[p0] = r0.l; /* Set the value */
539 p0.h = hi(PLL_STAT);
540 p0.l = lo(PLL_STAT);
547 p0.h = hi(PLL_DIV);
548 p0.l = lo(PLL_DIV);
549 w[p0] = r0.l;
570 p0.h = hi(UART_GCTL);
571 p0.l = lo(UART_GCTL);
573 w[p0] = r0.L; /* To Turn off UART clocks */
576 p0.h = hi(UART_LCR);
577 p0.l = lo(UART_LCR);
579 w[p0] = r0.L; /* To enable DLL writes */
584 p0.h = hi(UART_DLL);
585 p0.l = lo(UART_DLL);
588 w[p0] = r0.L;
591 p0.h = hi(UART_DLH);
592 p0.l = lo(UART_DLH);
594 w[p0] = r1.L;
597 p0.h = hi(UART_GCTL);
598 p0.l = lo(UART_GCTL);
600 w[p0] = r0.L; /* To enable UART clock */
603 p0.h = hi(UART_LCR);
604 p0.l = lo(UART_LCR);
606 w[p0] = r0.L; /* To Turn on UART */
609 p0.h = hi(UART_GCTL);
610 p0.l = lo(UART_GCTL);
612 w[p0] = r0.L; /* To Turn on UART Clocks */