Lines Matching refs:DMAEN
416 dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
436 dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
705 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
706 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
708 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
709 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
713 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
714 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
716 bfin_write_MDMA_S0_CONFIG(DMAEN);
717 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
781 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
782 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
811 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
812 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
845 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
846 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
875 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
876 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
909 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
910 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
939 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
940 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);