Lines Matching defs:irqno
89 s3c_irq_wake(unsigned int irqno, unsigned int state)
91 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
97 state ? "enabled" : "disabled", irqno);
108 s3c_irqext_wake(unsigned int irqno, unsigned int state)
110 unsigned long bit = 1L << (irqno - EXTINT_OFF);
116 state ? "enabled" : "disabled", irqno);
133 s3c_irq_mask(unsigned int irqno)
137 irqno -= IRQ_EINT0;
140 mask |= 1UL << irqno;
145 s3c_irq_ack(unsigned int irqno)
147 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
154 s3c_irq_maskack(unsigned int irqno)
156 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
168 s3c_irq_unmask(unsigned int irqno)
172 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
173 irqdbf2("s3c_irq_unmask %d\n", irqno);
175 irqno -= IRQ_EINT0;
178 mask &= ~(1UL << irqno);
199 s3c_irqext_mask(unsigned int irqno)
203 irqno -= EXTINT_OFF;
206 mask |= ( 1UL << irqno);
211 s3c_irqext_ack(unsigned int irqno)
217 bit = 1UL << (irqno - EXTINT_OFF);
228 if (irqno <= IRQ_EINT7 ) {
238 s3c_irqext_unmask(unsigned int irqno)
242 irqno -= EXTINT_OFF;
245 mask &= ~( 1UL << irqno);
360 s3c_irq_uart0_mask(unsigned int irqno)
362 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
366 s3c_irq_uart0_unmask(unsigned int irqno)
368 s3c_irqsub_unmask(irqno, INTMSK_UART0);
372 s3c_irq_uart0_ack(unsigned int irqno)
374 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
387 s3c_irq_uart1_mask(unsigned int irqno)
389 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
393 s3c_irq_uart1_unmask(unsigned int irqno)
395 s3c_irqsub_unmask(irqno, INTMSK_UART1);
399 s3c_irq_uart1_ack(unsigned int irqno)
401 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
414 s3c_irq_uart2_mask(unsigned int irqno)
416 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
420 s3c_irq_uart2_unmask(unsigned int irqno)
422 s3c_irqsub_unmask(irqno, INTMSK_UART2);
426 s3c_irq_uart2_ack(unsigned int irqno)
428 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
441 s3c_irq_adc_mask(unsigned int irqno)
443 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
447 s3c_irq_adc_unmask(unsigned int irqno)
449 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
453 s3c_irq_adc_ack(unsigned int irqno)
455 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
664 int irqno;
712 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
715 switch (irqno) {
724 set_irq_chip(irqno, &s3c_irq_level_chip);
725 set_irq_handler(irqno, handle_level_irq);
734 //irqdbf("registering irq %d (s3c irq)\n", irqno);
735 set_irq_chip(irqno, &s3c_irq_chip);
736 set_irq_handler(irqno, handle_edge_irq);
737 set_irq_flags(irqno, IRQF_VALID);
753 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
754 irqdbf("registering irq %d (ext int)\n", irqno);
755 set_irq_chip(irqno, &s3c_irq_eint0t4);
756 set_irq_handler(irqno, handle_edge_irq);
757 set_irq_flags(irqno, IRQF_VALID);
760 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
761 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
762 set_irq_chip(irqno, &s3c_irqext_chip);
763 set_irq_handler(irqno, handle_edge_irq);
764 set_irq_flags(irqno, IRQF_VALID);
771 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
772 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
773 set_irq_chip(irqno, &s3c_irq_uart0);
774 set_irq_handler(irqno, handle_level_irq);
775 set_irq_flags(irqno, IRQF_VALID);
778 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
779 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
780 set_irq_chip(irqno, &s3c_irq_uart1);
781 set_irq_handler(irqno, handle_level_irq);
782 set_irq_flags(irqno, IRQF_VALID);
785 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
786 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
787 set_irq_chip(irqno, &s3c_irq_uart2);
788 set_irq_handler(irqno, handle_level_irq);
789 set_irq_flags(irqno, IRQF_VALID);
792 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
793 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
794 set_irq_chip(irqno, &s3c_irq_adc);
795 set_irq_handler(irqno, handle_edge_irq);
796 set_irq_flags(irqno, IRQF_VALID);