Lines Matching refs:timer
56 /* timer control reg bits */
68 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
134 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
136 return readl(timer->io_base + reg);
139 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
141 writel(value, timer->io_base + reg);
142 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
146 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
151 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
160 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
164 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
165 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
166 omap_dm_timer_wait_for_reset(timer);
168 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
171 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
174 if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
178 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
180 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
183 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
185 omap_dm_timer_enable(timer);
186 omap_dm_timer_reset(timer);
191 struct omap_dm_timer *timer = NULL;
200 timer = &dm_timers[i];
201 timer->reserved = 1;
206 if (timer != NULL)
207 omap_dm_timer_prepare(timer);
209 return timer;
214 struct omap_dm_timer *timer;
220 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
226 timer = &dm_timers[id-1];
227 timer->reserved = 1;
230 omap_dm_timer_prepare(timer);
232 return timer;
235 void omap_dm_timer_free(struct omap_dm_timer *timer)
237 omap_dm_timer_enable(timer);
238 omap_dm_timer_reset(timer);
239 omap_dm_timer_disable(timer);
241 WARN_ON(!timer->reserved);
242 timer->reserved = 0;
245 void omap_dm_timer_enable(struct omap_dm_timer *timer)
247 if (timer->enabled)
250 omap_dm_clk_enable(timer->fclk);
251 omap_dm_clk_enable(timer->iclk);
253 timer->enabled = 1;
256 void omap_dm_timer_disable(struct omap_dm_timer *timer)
258 if (!timer->enabled)
261 omap_dm_clk_disable(timer->iclk);
262 omap_dm_clk_disable(timer->fclk);
264 timer->enabled = 0;
267 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
269 return timer->irq;
274 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
291 /* If any active timer is using ARMXOR return modified mask */
309 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
311 return timer->fclk;
323 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
325 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
328 void omap_dm_timer_start(struct omap_dm_timer *timer)
332 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
335 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
339 void omap_dm_timer_stop(struct omap_dm_timer *timer)
343 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
346 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
352 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
354 int n = (timer - dm_timers) << 1;
364 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
369 clk_disable(timer->fclk);
370 clk_set_parent(timer->fclk, dm_source_clocks[source]);
371 clk_enable(timer->fclk);
380 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
385 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
390 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
391 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
392 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
395 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
400 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
405 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
406 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
410 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
415 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
423 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
426 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
430 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
436 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
439 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
442 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
443 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
446 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
450 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
455 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
457 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
460 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
464 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
469 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
471 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
479 struct omap_dm_timer *timer;
481 timer = &dm_timers[i];
483 if (!timer->enabled)
486 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
496 struct omap_dm_timer *timer;
517 timer = &dm_timers[i];
518 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
521 timer->iclk = clk_get(NULL, clk_name);
523 timer->fclk = clk_get(NULL, clk_name);