Lines Matching defs:lch
58 void (* callback)(int lch, u16 ch_status, void *data);
113 static void clear_lch_regs(int lch)
116 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
122 void omap_set_dma_priority(int lch, int dst_port, int priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
155 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
159 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
163 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
164 OMAP_DMA_CSDP_REG(lch) |= data_type;
167 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
169 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
171 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
173 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
177 u32 val = OMAP_DMA_CCR_REG(lch);
203 OMAP_DMA_CCR_REG(lch) = val;
206 OMAP_DMA_CEN_REG(lch) = elem_count;
207 OMAP_DMA_CFN_REG(lch) = frame_count;
210 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
221 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
234 OMAP1_DMA_CCR2_REG(lch) = w;
236 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
239 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
240 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
243 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
246 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
255 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
260 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
261 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
264 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
265 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
268 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
269 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
273 OMAP2_DMA_CSSA_REG(lch) = src_start;
275 OMAP_DMA_CSEI_REG(lch) = src_ei;
276 OMAP_DMA_CSFI_REG(lch) = src_fi;
279 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
281 omap_set_dma_transfer_params(lch, params->data_type,
285 omap_set_dma_src_params(lch, params->src_port,
289 omap_set_dma_dest_params(lch, params->dst_port,
294 void omap_set_dma_src_index(int lch, int eidx, int fidx)
300 OMAP_DMA_CSEI_REG(lch) = eidx;
301 OMAP_DMA_CSFI_REG(lch) = fidx;
304 void omap_set_dma_src_data_pack(int lch, int enable)
306 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
308 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
311 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
314 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
345 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
349 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
354 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
355 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
358 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
359 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
362 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
363 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
367 OMAP2_DMA_CDSA_REG(lch) = dest_start;
369 OMAP_DMA_CDEI_REG(lch) = dst_ei;
370 OMAP_DMA_CDFI_REG(lch) = dst_fi;
373 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
379 OMAP_DMA_CDEI_REG(lch) = eidx;
380 OMAP_DMA_CDFI_REG(lch) = fidx;
383 void omap_set_dma_dest_data_pack(int lch, int enable)
385 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
387 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
390 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
393 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
423 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
426 static inline void omap_enable_channel_irq(int lch)
432 status = OMAP_DMA_CSR_REG(lch);
434 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
437 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
439 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
442 static void omap_disable_channel_irq(int lch)
445 OMAP_DMA_CICR_REG(lch) = 0;
448 void omap_enable_dma_irq(int lch, u16 bits)
450 dma_chan[lch].enabled_irqs |= bits;
453 void omap_disable_dma_irq(int lch, u16 bits)
455 dma_chan[lch].enabled_irqs &= ~bits;
458 static inline void enable_lnk(int lch)
461 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
464 if (dma_chan[lch].next_lch != -1)
465 OMAP_DMA_CLNK_CTRL_REG(lch) =
466 dma_chan[lch].next_lch | (1 << 15);
469 static inline void disable_lnk(int lch)
473 OMAP_DMA_CICR_REG(lch) = 0;
475 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
479 omap_disable_channel_irq(lch);
481 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
484 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
487 static inline void omap2_enable_irq_lch(int lch)
495 val |= 1 << lch;
500 void (* callback)(int lch, u16 ch_status, void *data),
568 void omap_free_dma(int lch)
573 if (dma_chan[lch].dev_id == -1) {
575 lch);
579 dma_chan[lch].dev_id = -1;
580 dma_chan[lch].next_lch = -1;
581 dma_chan[lch].callback = NULL;
586 OMAP_DMA_CICR_REG(lch) = 0;
588 OMAP_DMA_CCR_REG(lch) = 0;
595 val &= ~(1 << lch);
599 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
600 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
603 OMAP_DMA_CICR_REG(lch) = 0;
606 OMAP_DMA_CCR_REG(lch) = 0;
607 omap_clear_dma(lch);
615 void omap_clear_dma(int lch)
623 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
626 status = OMAP_DMA_CSR_REG(lch);
631 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
639 void omap_start_dma(int lch)
641 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
645 dma_chan_link_map[lch] = 1;
647 enable_lnk(lch);
650 cur_lch = dma_chan[lch].next_lch;
666 /* Errata: Need to write lch even if not using chaining */
667 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
670 omap_enable_channel_irq(lch);
675 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
678 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
680 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
683 void omap_stop_dma(int lch)
685 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
686 int next_lch, cur_lch = lch;
708 OMAP_DMA_CICR_REG(lch) = 0;
710 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
711 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
718 int omap_set_dma_callback(int lch,
719 void (* callback)(int lch, u16 ch_status, void *data),
724 if (lch < 0)
728 if (dma_chan[lch].dev_id == -1) {
733 dma_chan[lch].callback = callback;
734 dma_chan[lch].data = data;
748 dma_addr_t omap_get_dma_src_pos(int lch)
753 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
754 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
757 offset = OMAP_DMA_CSAC_REG(lch);
770 dma_addr_t omap_get_dma_dst_pos(int lch)
775 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
776 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
779 offset = OMAP2_DMA_CDSA_REG(lch);
789 int omap_get_dma_src_addr_counter(int lch)
791 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
796 int lch;
803 for (lch = 0; lch < dma_chan_count; lch++)
804 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
930 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);