Lines Matching refs:and
17 * abort here if the I-TLB and D-TLB aren't seeing the same
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
34 and r7, r8, #15 << 24
66 and r6, r8, r7
67 and r2, r8, r7, lsl #1
69 and r2, r8, r7, lsl #2
71 and r2, r8, r7, lsl #3
75 and r6, r6, #15 @ r6 = no. of registers to transfer.
76 and r5, r8, #15 << 16 @ Extract 'n' from instruction
88 and r5, r8, #0x00f @ get Rm / low nibble of immediate value
94 and r5, r8, #15 << 16 @ Extract 'n' from instruction
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction
120 and r7, r8, #15 @ Extract 'm' from instruction
124 and r7, r8, #0x70 @ get shift type
165 and r7, r8, #15 << 12
196 and r6, r8, #0x55 @ hweight8(r8) + R bit
197 and r2, r8, #0xaa
199 and r2, r6, #0xcc
200 and r6, r6, #0x33
204 and r6, r6, #15 @ number of regs to transfer
213 and r6, r8, #0x55 @ hweight8(r8)
214 and r2, r8, #0xaa
216 and r2, r6, #0xcc
217 and r6, r6, #0x33
220 and r5, r8, #7 << 8
222 and r6, r6, #15 @ number of regs to transfer