Lines Matching refs:to
4 * Omap2 specific functions that need to be run in internal SRAM
21 * along with this program; if not, write to the Free Software
55 str r3, [r2] @ go to L1-freq operation
65 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
66 mvn r9, #0x4 @ mask to get clear bit2
70 str r10, [r11] @ commit to DLLA_CTRL
71 bl i_dll_wait @ wait for dll to lock
78 mov r9, #0x0 @ shift back to L0-voltage
83 str r3, [r2] @ go to L0-freq operation
86 sub r11, r11, #0x4 @ move from status to ctrl
88 subeq r11, r11, #0x8 @ possibly back to DLLA
92 add r11, r11, #0x8 @ move to DLLB_CTRL addr
109 * shift up or down voltage, use R9 as input to tell level.
110 * wait for it to finish, use 32k sync counter, 1tick=31uS.
116 and r5, r5, r6 @ apply mask to clear bits
121 str r5, [r4] @ Force transition to L1
130 mov pc, lr @ back to caller.
161 cmp r0, #0x1 @ going to half speed?
166 cmp r0, #0x1 @ going to half speed (post branch link)
167 moveq r5, r5, lsr #1 @ divide by 2 if to half
168 movne r5, r5, lsl #1 @ mult by 2 if to full
188 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
191 /* With DDR, we need to take care of the DLL for the frequency change */
194 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
195 str r1, [r2] @ commit to SDRC_DLLB_CTRL
204 * shift up or down voltage, use R9 as input to tell level.
205 * wait for it to finish, use 32k sync counter, 1tick=31uS.
211 and r8, r8, r7 @ apply mask to clear bits
216 str r8, [r10] @ Force transition to L1
225 mov pc, lr @ back to caller
247 stmfd sp!, {r0-r12, lr} @ regs to stack
258 str r7, [r8] @ go to fast relock
304 mvn r9, #0x4 @ mask to get clear bit2
307 str r10, [r11] @ commit to DLLA_CTRL
308 add r11, r11, #0x8 @ move to dllb