Lines Matching defs:core_if
198 static int check_parameters(dwc_otg_core_if_t *core_if)
359 if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
363 if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
364 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
365 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
366 (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
376 (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
377 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
378 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
379 (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
384 ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
389 ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
403 (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
407 (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
408 core_if->hwcfg3.b.dfifo_depth);
412 (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
413 dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
417 (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
418 (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
422 (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
423 dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
427 (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
428 (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
432 (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
433 ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
437 (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
438 ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
442 (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
443 ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
447 (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
448 (core_if->hwcfg2.b.num_host_chan + 1));
452 (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
453 core_if->hwcfg2.b.num_dev_ep);
471 ((core_if->hwcfg2.b.hs_phy_type == 1) ||
472 (core_if->hwcfg2.b.hs_phy_type == 3))) {
476 ((core_if->hwcfg2.b.hs_phy_type == 2) ||
477 (core_if->hwcfg2.b.hs_phy_type == 3))) {
481 (core_if->hwcfg2.b.fs_phy_type == 1)) {
488 if (core_if->hwcfg2.b.hs_phy_type) {
489 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
490 (core_if->hwcfg2.b.hs_phy_type == 1)) {
521 (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
533 if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
538 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
544 ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
555 if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
560 dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
566 ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
573 ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
577 ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
595 retval = dwc_otg_handle_common_intr(otg_dev->core_if);
640 if (otg_dev->core_if) {
641 dwc_otg_cil_remove(otg_dev->core_if);
771 otg_dev->core_if = dwc_otg_cil_init(otg_dev->base,
774 otg_dev->core_if->snpsid = snpsid;
776 if (!otg_dev->core_if) {
785 if (check_parameters(otg_dev->core_if)) {
799 dwc_otg_disable_global_interrupts(otg_dev->core_if);
820 dwc_otg_core_init(otg_dev->core_if);
849 dwc_otg_enable_global_interrupts(otg_dev->core_if);