Lines Matching refs:params
49 if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL)
193 _core_if->params.dma_burst_size = _params->dma_burst_size;
194 _core_if->params.speed = _params->speed;
196 _core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1);
198 _core_if->params.max_transfer_size = _params->max_transfer_size;
201 _core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
203 _core_if->params.max_packet_count= _params->max_packet_count;
204 _core_if->params.phy_utmi_width = _params->phy_utmi_width;
205 _core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
206 _core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
207 _core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
208 _core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
211 _core_if->params.thr_ctl = _params->thr_ctl;
212 _core_if->params.tx_thr_length = _params->tx_thr_length;
213 _core_if->params.rx_thr_length = _params->rx_thr_length;
243 usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
250 switch (_core_if->params.dma_burst_size)
295 _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
296 _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
297 IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
298 IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
300 _core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
304 _core_if->params.tx_fifo_size[i] =
308 _core_if->params.tx_fifo_size[i+1] =
315 IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]);
317 IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]);
319 IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]);
325 if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
326 _core_if->params.data_fifo_size = _params->data_fifo_size;
329 if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
330 _core_if->params.rx_fifo_size = _params->rx_fifo_size;
331 if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
332 _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
333 ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
336 if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i])
337 _core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i];
339 txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
341 if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
342 _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
343 txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
345 txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
348 if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size)
349 _core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
350 txfifosize.b.depth=_core_if->params.tx_fifo_size[i];
352 txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i];
355 if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
356 _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
357 txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
359 txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
362 if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size)
363 _core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
364 //txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1];
366 txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1];
374 IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);