Lines Matching defs:_dwc_otg_hcd
48 int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
52 dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if;
81 retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd);
84 retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd);
87 retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd);
93 retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd);
96 retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd);
99 retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd);
218 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
225 grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp);
227 hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
239 dwc_otg_read_packet(_dwc_otg_hcd->core_if,
265 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
268 dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
277 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
280 dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
288 int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
294 hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
295 hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
310 _dwc_otg_hcd->flags.b.port_connect_status_change = 1;
311 _dwc_otg_hcd->flags.b.port_connect_status = 1;
315 del_timer( &_dwc_otg_hcd->conn_timer );
330 dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params;
331 dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs;
332 dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if;
394 tasklet_schedule(_dwc_otg_hcd->reset_tasklet);
400 _dwc_otg_hcd->flags.b.port_reset_change = 1;
404 _dwc_otg_hcd->flags.b.port_enable_change = 1;
413 _dwc_otg_hcd->flags.b.port_over_current_change = 1;
419 dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
429 int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
438 haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
440 for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) {
442 retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i);
1759 int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num)
1771 hc = _dwc_otg_hcd->hc_ptr_array[_num];
1772 hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num];
1781 if (!_dwc_otg_hcd->core_if->dma_enable) {
1788 retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1797 retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1800 retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1803 retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1806 retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1809 retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1812 retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1815 retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1818 retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1821 retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
1824 retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);