Lines Matching refs:dwc_otg_module_params
93 static dwc_otg_core_params_t dwc_otg_module_params = {
173 ((dwc_otg_module_params._param_ < (_low_)) || \
174 (dwc_otg_module_params._param_ > (_high_)))
180 if (dwc_otg_module_params._param_ != -1) { \
183 dwc_otg_module_params._param_, _string_); \
184 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
214 if (dwc_otg_module_params.dma_burst_size != -1) {
225 dwc_otg_module_params.dma_burst_size);
226 dwc_otg_module_params.dma_burst_size = 32;
231 if (dwc_otg_module_params.phy_utmi_width != -1) {
236 dwc_otg_module_params.phy_utmi_width);
237 //dwc_otg_module_params.phy_utmi_width = 16;
238 dwc_otg_module_params.phy_utmi_width = 8;
246 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
249 dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
250 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
260 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
263 dwc_otg_module_params.dev_tx_fifo_size[i],
265 dwc_otg_module_params.dev_tx_fifo_size[i] =
287 if (dwc_otg_module_params._param_ == -1) { \
289 dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
304 DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \
307 dwc_otg_module_params._param_ = (_set_valid_); \
317 switch (dwc_otg_module_params.otg_cap) {
344 ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
359 ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
365 (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
370 (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
375 (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
380 (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
386 (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
391 (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
396 (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
401 (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
406 (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
411 (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
429 if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
435 else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
441 else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
464 (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
465 dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
469 ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
470 ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
484 (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
493 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
495 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
497 if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
499 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i);
502 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
509 ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
515 if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
517 dwc_otg_module_params.dev_tx_fifo_size[i] =
520 if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <=
524 "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i);
527 dwc_otg_module_params.dev_tx_fifo_size[i] =
724 dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params);
932 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
934 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
936 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
938 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
940 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
942 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
944 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
946 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
948 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
950 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
952 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
954 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
956 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
958 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
960 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
962 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
964 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
966 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
968 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
970 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
972 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
974 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
976 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
978 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
980 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
982 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
984 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
986 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
988 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
990 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
993 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
995 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
997 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
999 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1001 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1003 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1005 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1007 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1009 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1011 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1016 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1020 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1023 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1026 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1029 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1032 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1035 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1038 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1041 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1044 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1047 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1050 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1053 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1056 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1059 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1062 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1064 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1067 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1069 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);