Lines Matching defs:data
632 u32 data;
641 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
642 if (data & RTL8367_IA_STATUS_PHY_BUSY)
655 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
656 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
667 /* read data */
679 u32 data;
691 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
692 if (data & RTL8367_IA_STATUS_PHY_BUSY)
695 /* preapre data */
708 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
709 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
807 u32 data;
814 REG_RD(smi, RTL8367_CHIP_VER_REG, &data);
815 rlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) &
818 REG_RD(smi, RTL8367_CHIP_MODE_REG, &data);
819 mode = data & RTL8367_CHIP_MODE_MASK;
835 err = rtl8367_read_phy_reg(smi, 0, 6, &data);
839 if (data == 0x94eb) {
841 } else if (data == 0x2104) {
844 dev_err(smi->parent, "unknow phy data %04x\n", data);
863 u32 data;
869 REG_RD(smi, RTL8367_CHIP_RESET_REG, &data);
870 if (!(data & RTL8367_CHIP_RESET_HW))
1147 u32 addr, data;
1163 REG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data);
1165 if (data & RTL8367_MIB_CTRL_BUSY_MASK)
1168 if (data & RTL8367_MIB_CTRL_RESET_MASK)
1178 REG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data);
1179 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1189 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1204 for (i = 0; i < ARRAY_SIZE(data); i++)
1205 REG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]);
1208 vlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) &
1210 vlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) &
1212 vlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) &
1214 vlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) &
1223 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1233 data[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) <<
1235 data[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) <<
1237 data[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) <<
1239 data[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) <<
1242 for (i = 0; i < ARRAY_SIZE(data); i++)
1243 REG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]);
1258 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1267 for (i = 0; i < ARRAY_SIZE(data); i++)
1268 REG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]);
1270 vlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) &
1272 vlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) &
1274 vlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) &
1283 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1295 data[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) <<
1297 data[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) <<
1299 data[2] = 0;
1300 data[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) <<
1303 for (i = 0; i < ARRAY_SIZE(data); i++)
1304 REG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]);
1311 u32 data;
1317 REG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data);
1319 *val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) &
1387 u32 data = 0;
1393 rtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data);
1395 link->link = !!(data & RTL8367_PORT_STATUS_LINK);
1399 link->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX);
1400 link->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE);
1401 link->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE);
1402 link->aneg = !!(data & RTL8367_PORT_STATUS_NWAY);
1404 speed = (data & RTL8367_PORT_STATUS_SPEED_MASK);
1428 u32 data;
1430 rtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data);
1431 val->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >>
1682 dev_err(&pdev->dev, "no platform data specified\n");