Lines Matching defs:data
247 u32 data;
253 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
256 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
295 u32 phy_no, u32 page, u32 addr, u32 *data)
322 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
330 u32 phy_no, u32 page, u32 addr, u32 data)
353 ret = rtl8366_smi_write_reg(smi, reg, data);
365 u32 addr, data;
379 data = 0; /* writing data will be discard by ASIC */
380 err = rtl8366_smi_write_reg(smi, addr, data);
385 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
389 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
392 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
397 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
401 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
411 u32 data[3];
435 &data[i]);
441 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
443 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
444 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
452 u32 data[3];
462 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
463 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
466 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
471 data[i]);
486 u32 data[3];
498 &data[i]);
503 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
504 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
506 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
508 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
509 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
517 u32 data[3];
529 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
532 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
535 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
540 data[i]);
550 u32 data;
557 &data);
561 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
627 u32 data;
629 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
631 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
655 u32 data;
657 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
658 val->value.i = !data;
689 u32 data = 0;
696 &data);
699 data = data >> 8;
701 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
705 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
706 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
707 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
708 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
710 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
734 u32 data;
744 data = val->value.i << 4;
748 data = val->value.i << (val->port_vlan * 4);
751 return rtl8366_smi_rmwr(smi, reg, mask, data);
759 u32 data = 0;
764 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
765 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
775 u32 mask, data;
782 data = mask;
784 data = 0;
786 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
794 u32 data;
799 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
800 if (data & (1 << val->port_vlan))
834 u32 data;
839 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
840 data &= RTL8366RB_IB_BDTH_MASK;
841 if (data < RTL8366RB_IB_BDTH_MASK)
842 data += 1;
844 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
877 u32 data;
882 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
883 data &= RTL8366RB_EB_BDTH_MASK;
884 if (data < RTL8366RB_EB_BDTH_MASK)
885 data += 1;
887 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
897 u32 data;
900 data = RTL8366RB_QOS_MASK;
902 data = 0;
904 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
912 u32 data;
914 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
915 if (data & RTL8366RB_QOS_MASK)
1184 dev_err(&pdev->dev, "no platform data specified\n");