Lines Matching refs:regVal
1105 MV_U32 regVal;
1107 regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo));
1108 regVal &= ~ETH_TX_INTR_COAL_ALL_MASK;
1109 regVal |= ETH_TX_INTR_COAL_MASK(coal);
1112 MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal);
1144 MV_U32 regVal, coal, usec;
1149 regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo));
1150 coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET);
1157 regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo));
1158 coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET);
1161 if(regVal & ETH_RX_INTR_COAL_MSB_MASK)
2899 MV_U32 regVal;
2908 regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
2909 regVal &= (~ETH_PORT_RESET_MASK);
2910 MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal);
2916 MV_U32 regVal;
2919 regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port));
2920 if( (regVal & ETH_PORT_ENABLE_MASK) != 0)
2923 port, regVal);
2928 regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
2929 MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK);
2935 MV_U32 regVal;
2937 regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port));
2939 regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */);
2940 regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK);
2942 MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal);