Lines Matching defs:data
84 * has its DRAM on DIMMs it will use its EEPROM to extract SPD data
223 MV_U8 data[SPD_SIZE];
226 memset(data, 0, SPD_SIZE);
236 if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) )
248 spdChecksum += data[i];
251 if ((spdChecksum & 0xff) != data[63])
254 (MV_U32)(spdChecksum & 0xff), data[63]));
271 if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) )
306 MV_U8 data[SPD_SIZE];
315 memset(data, 0, SPD_SIZE);
326 if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) )
338 spdChecksum += data[i];
341 if ((spdChecksum & 0xff) != data[63])
344 (MV_U32)(spdChecksum & 0xff), data[63]));
354 pDimmInfo->spdRawData[i] = data[i];
355 DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i]));
361 switch (data[DIMM_MEM_TYPE])
382 pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM];
386 pDimmInfo->numOfColAddr = data[DIMM_COL_NUM];
390 pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM];
399 pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH];
403 pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]);
406 pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE];
411 pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL];
416 pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH];
420 pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH];
438 pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP];
443 pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM];
470 pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL];
477 pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION];
483 pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN];
489 cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]);
493 cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]);
495 pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME];
498 pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE];
501 pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY];
504 pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH];
509 pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY];
514 pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME];
519 pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY];
524 pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY];
529 pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD];
695 /* go over the first 35 I2C data bytes */