Lines Matching refs:MV_U32
115 MV_U32 numOfRowAddr;
116 MV_U32 numOfColAddr;
117 MV_U32 dataWidth;
118 MV_U32 errorCheckType; /* ECC , PARITY..*/
119 MV_U32 sdramWidth; /* 4,8,16 or 32 */
120 MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
121 MV_U32 burstLengthSupported;
122 MV_U32 numOfBanksOnEachDevice;
123 MV_U32 suportedCasLatencies;
124 MV_U32 refreshInterval;
127 MV_U32 minCycleTimeAtMaxCasLatPs;
128 MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
129 MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
130 MV_U32 minRowPrechargeTime;
131 MV_U32 minRowActiveToRowActive;
132 MV_U32 minRasToCasDelay;
133 MV_U32 minRasPulseWidth;
134 MV_U32 minWriteRecoveryTime; /* DDR2 only */
135 MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
136 MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
137 MV_U32 minRefreshToActiveCmd; /* DDR2 only */
140 MV_U32 size;
141 MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */
142 MV_U32 numberOfDevices;
154 MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable);
157 MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum);
158 MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum);
159 MV_U32 mvDramIfSizeGet(MV_VOID);
160 MV_U32 mvDramIfCalGet(void);
161 MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold);
164 MV_U32 mvDramIfGetFirstCS(void);
165 MV_U32 mvDramIfGetCSorder(MV_U32 csOrder );
166 MV_U32 mvDramCsSizeGet(MV_U32 csNum);