Lines Matching refs:mov
258 mov r11, LR /* Save link register */
259 mov r10, r2
263 mov r5, #1
273 mov r6, #0
303 mov sp, #0
306 mov r2, r10
307 mov PC, r11 /* r11 is saved link register */
361 mov r11, LR /* Save link register */
363 mov r5, #1
439 mov r8, r6
442 mov r6, r8 /* Do not swap r8 content */
515 mov r6, #0x5 /* 'NOP' command */
528 mov r6, #0x3 /* Mode Register Set command */
554 mov r8, r7
555 mov r8, r8, LSR #20 /* Move density 20 bits to the right */
558 mov r6, #0x00
562 mov r6, #0x10
566 mov r6, #0x20
584 mov r6, #0x5 /* 'NOP' command */
598 mov r6, #0x4 /* Extended Mode Register Set command */
678 mov r5, r6
679 mov r5, r5, LSL #9
680 mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
703 mov r5, r6
704 mov r5, r5, LSL #9
705 mov r5, r5, LSR #26
788 mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
901 mov PC, r11 /* r11 is saved link register */
912 mov r13, LR /* Save link register */
914 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
915 mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
917 mov r8, r7 /* r8 save number of rows */
919 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
920 mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
924 mov r7, #0x1
925 mov r8, r7, LSL r8 /* r8 = (1 << r8) */
927 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
928 mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
932 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
933 mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
937 mov PC, r13
941 mov r13, LR /* Save link register */
944 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
945 mov r7, #SDRAM_WIDTH_OFFSET
948 mov PC, r13
952 mov r13, LR /* Save link register */
955 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
956 mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
959 mov PC, r13
966 mov r13, LR /* Save link register */
973 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
974 mov r7, #SDRAM_MODULES_ATTR_OFFSET
979 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
980 mov r7, #DIMM_TYPE_INFO_OFFSET
985 mov PC, r13