Lines Matching refs:MV_U32
119 MV_U32 numOfRowAddr;
120 MV_U32 numOfColAddr;
121 MV_U32 dataWidth;
122 MV_U32 errorCheckType; /* ECC , PARITY..*/
123 MV_U32 sdramWidth; /* 4,8,16 or 32 */
124 MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
125 MV_U32 burstLengthSupported;
126 MV_U32 numOfBanksOnEachDevice;
127 MV_U32 suportedCasLatencies;
128 MV_U32 refreshInterval;
131 MV_U32 minCycleTimeAtMaxCasLatPs;
132 MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
133 MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
134 MV_U32 minRowPrechargeTime;
135 MV_U32 minRowActiveToRowActive;
136 MV_U32 minRasToCasDelay;
137 MV_U32 minRasPulseWidth;
138 MV_U32 minWriteRecoveryTime; /* DDR2 only */
139 MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
140 MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
141 MV_U32 minRefreshToActiveCmd; /* DDR2 only */
144 MV_U32 size;
145 MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */
146 MV_U32 numberOfDevices;
164 MV_STATUS mvDramIfDetect(MV_U32 forcedCl);
170 MV_32 mvDramIfBankSizeGet(MV_U32 bankNum);
171 MV_32 mvDramIfBankBaseGet(MV_U32 bankNum);
176 MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable);