Lines Matching defs:bankInfo
135 MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS];
161 if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i]))
164 if(bankInfo[i].memoryType == MEM_TYPE_SDRAM)
170 if(bankInfo[i].registeredAddrAndControlInputs !=
171 bankInfo[0].registeredAddrAndControlInputs)
183 dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16);
184 size = ((bankInfo[i].size << 20) / (dimmW/deviceW));
229 bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies;
242 bankInfo[i].size = 0; /* Mark this bank as non exist */
248 minCas = minCasCalc(&bankInfo[0], busClk, forcedCl);
267 temp = sdramConfigRegCalc(&bankInfo[0], busClk);
285 temp = sdramExtModeRegCalc(&bankInfo[0]);
294 temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas);
303 temp = sdramAddrCtrlRegCalc(&bankInfo[0]);
312 temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk);
321 temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk);
332 sdramDDr2OdtConfig(bankInfo);