Lines Matching refs:MV_U32
150 MV_U32 numOfRowAddr;
151 MV_U32 numOfColAddr;
152 MV_U32 numOfModuleBanks;
153 MV_U32 dataWidth;
154 MV_U32 errorCheckType; /* ECC , PARITY..*/
155 MV_U32 sdramWidth; /* 4,8,16 or 32 */
156 MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */
157 MV_U32 burstLengthSupported;
158 MV_U32 numOfBanksOnEachDevice;
159 MV_U32 suportedCasLatencies;
160 MV_U32 refreshInterval;
161 MV_U32 dimmBankDensity;
162 MV_U32 dimmTypeInfo; /* DDR2 only */
163 MV_U32 dimmAttributes;
166 MV_U32 minCycleTimeAtMaxCasLatPs;
167 MV_U32 minCycleTimeAtMaxCasLatMinus1Ps;
168 MV_U32 minCycleTimeAtMaxCasLatMinus2Ps;
169 MV_U32 minRowPrechargeTime;
170 MV_U32 minRowActiveToRowActive;
171 MV_U32 minRasToCasDelay;
172 MV_U32 minRasPulseWidth;
173 MV_U32 minWriteRecoveryTime; /* DDR2 only */
174 MV_U32 minWriteToReadCmdDelay; /* DDR2 only */
175 MV_U32 minReadToPrechCmdDelay; /* DDR2 only */
176 MV_U32 minRefreshToActiveCmd; /* DDR2 only */
179 MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */
180 MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */
181 MV_U32 numberOfDevices;
186 MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo);
187 MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo);
188 MV_VOID dimmSpdPrint(MV_U32 dimmNum);