Lines Matching defs:mii
17 #include <linux/mii.h>
366 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
378 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
379 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
380 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
386 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
397 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
398 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
399 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
403 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
408 ret = __ar7240sw_reg_read(mii, reg_addr);
414 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
417 __ar7240sw_reg_write(mii, reg_addr, reg_val);
421 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
426 t = __ar7240sw_reg_read(mii, reg);
429 __ar7240sw_reg_write(mii, reg, t);
435 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
440 t = __ar7240sw_reg_read(mii, reg);
442 __ar7240sw_reg_write(mii, reg, t);
446 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
454 t = __ar7240sw_reg_read(mii, reg);
464 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
470 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
475 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
491 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
492 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
495 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
501 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
518 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
519 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
528 struct mii_bus *mii = as->mii_bus;
535 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
540 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
553 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
576 struct mii_bus *mii = as->mii_bus;
579 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
584 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
588 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
593 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
596 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
599 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
603 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
608 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
615 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
620 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
624 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
629 struct mii_bus *mii = as->mii_bus;
641 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
644 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
649 ar7240sw_phy_write(mii, i, MII_ADVERTISE,
652 ar7240sw_phy_write(mii, i, MII_BMCR,
663 struct mii_bus *mii = as->mii_bus;
671 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
679 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
716 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
723 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
724 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
731 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
737 struct mii_bus *mii = as->mii_bus;
741 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
744 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
867 struct mii_bus *mii = as->mii_bus;
868 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
879 struct mii_bus *mii = as->mii_bus;
880 v = ar7240sw_reg_read(mii, AR7240_REG_GLOBAL_CTRL);
892 struct mii_bus *mii = as->mii_bus;
900 v = ar7240sw_reg_read(mii, AR934X_REG_PORT_CONTROL(i));
903 ar7240sw_reg_write(mii, AR934X_REG_PORT_CONTROL(i), v);
906 v = ar7240sw_reg_read(mii, AR934X_REG_QM_CTRL);
908 ar7240sw_reg_write(mii, AR934X_REG_QM_CTRL, v);
910 v = ar7240sw_reg_read(mii, AR934X_REG_FLOOD_MASK);
913 ar7240sw_reg_write(mii, AR934X_REG_FLOOD_MASK, v);
917 v = ar7240sw_reg_read(mii, AR934X_REG_PORT_CONTROL(i));
920 ar7240sw_reg_write(mii, AR934X_REG_PORT_CONTROL(i), v);
923 v = ar7240sw_reg_read(mii, AR934X_REG_QM_CTRL);
925 ar7240sw_reg_write(mii, AR934X_REG_QM_CTRL, v);
927 v = ar7240sw_reg_read(mii, AR934X_REG_FLOOD_MASK);
930 ar7240sw_reg_write(mii, AR934X_REG_FLOOD_MASK, v);
939 struct mii_bus *mii = as->mii_bus;
941 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
947 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
950 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
1016 struct mii_bus *mii = as->mii_bus;
1022 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
1133 struct mii_bus *mii = ag->mii_bus;
1141 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1142 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1154 as->mii_bus = mii;
1159 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1170 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1173 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1182 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,