Lines Matching refs:dev
255 static void atm_init_parameters(amazon_atm_dev_t *dev)
258 dev->ports[0].enable = port_enable0;
259 dev->ports[0].max_conn = port_max_conn0;
260 dev->ports[0].tx_max_cr = port_cell_rate_up0;
262 dev->ports[1].enable = port_enable1;
263 dev->ports[1].max_conn = port_max_conn1;
264 dev->ports[1].tx_max_cr = port_cell_rate_up1;
268 dev->aal5.padding_byte = a5_fill_pattern;
269 dev->aal5.tx_max_sdu = a5s_mtu;
270 dev->aal5.rx_max_sdu = a5r_mtu;
273 dev->cbm.nrt_thr = cbm_nrt;
274 dev->cbm.clp0_thr = cbm_clp0;
275 dev->cbm.clp1_thr = cbm_clp1;
276 dev->cbm.free_cell_cnt = cbm_free_cell_no;
279 dev->qsb.tau = qsb_tau;
280 dev->qsb.tstepc =qsb_tstep;
281 dev->qsb.sbl = qsb_srvm;
284 dev->cbm.mem_addr = NULL;
285 dev->cbm.qd_addr = NULL;
670 //skb->dev=vcc->dev;
1504 amazon_atm_port_t * dev;
1505 dev = &g_atm_dev.ports[itf];
1515 while ( (qid<tmp1+dev->max_conn)
1520 if ( tmp1+dev->max_conn == qid)
2082 static void atm_constructor(amazon_atm_dev_t * dev)
2085 memset(dev,0,sizeof(amazon_atm_dev_t));
2086 atm_init_parameters(dev);
2089 //dev->queues[i].vcc=NULL;
2090 dev->queues[i].free = 1;
2093 dev->ports[i].tx_rem_cr = dev->ports[i].tx_max_cr;
2096 atomic_set(&dev->dma_tx_free_0,1); //initially there should be free descriptors
2116 static inline int atm_init_hard(amazon_atm_dev_t * dev)
2133 if (dev->cbm.mem_addr == NULL){
2134 dev->cbm.allocated = 1;
2135 mem_addr = (u8 *)__get_free_pages(GFP_KERNEL, get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1));
2137 dev->cbm.mem_addr = mem_addr;
2142 if (dev->cbm.qd_addr == NULL){
2148 dev->cbm.qd_addr_free = (u8*) (((unsigned long) qd_addr));
2149 dev->cbm.qd_addr = (u8*) (((unsigned long) qd_addr) | 0x8000);
2156 dev->cbm.qd_addr = qd_addr;
2163 mem_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.mem_addr);
2164 qd_addr = (u8 *)KSEG1ADDR((unsigned long)dev->cbm.qd_addr);
2167 memset_io(mem_addr, 0, CBM_CELL_SIZE * dev->cbm.free_cell_cnt);
2169 for(i=1;i<dev->cbm.free_cell_cnt;i++){
2176 AMAZON_WRITE_REGISTER_L(CPHYSADDR((mem_addr + CBM_CELL_SIZE * (dev->cbm.free_cell_cnt-1))), qd_addr);
2180 AMAZON_WRITE_REGISTER_L(dev->cbm.free_cell_cnt,(qd_addr + 8));
2187 AMAZON_WRITE_REGISTER_L(((dev->cbm.nrt_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_NRTTHR_ADDR);
2188 AMAZON_WRITE_REGISTER_L(((dev->cbm.clp0_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP0THR_ADDR);
2189 AMAZON_WRITE_REGISTER_L(((dev->cbm.clp1_thr&CBM_THR_MASK)|CBM_WM_3_1), CBM_CLP1THR_ADDR);
2203 tmp1 = dev->ports[0].max_conn?dev->ports[0].max_conn-1:0;
2206 tmp1+=dev->ports[i].max_conn;
2209 dev->cbm.max_q_off = tmp1+1;
2224 AMAZON_WRITE_REGISTER_L(dev->qsb.tau, QSB_TAU_ADDR);
2226 AMAZON_WRITE_REGISTER_L(dev->qsb.sbl, QSB_SBL_ADDR);
2228 AMAZON_WRITE_REGISTER_L(dev->qsb.tstepc>>1, QSB_CONFIG_ADDR);
2232 if ( (dev->ports[i].enable) && (dev->ports[i].tx_max_cr!=0) ){
2233 tmp1 = ((qsb_clk * dev->qsb.tstepc) >>1) / dev->ports[i].tx_max_cr;
2271 AMAZON_WRITE_REGISTER_L(dev->aal5.tx_max_sdu,AAL5_SMFL_ADDR);
2272 AMAZON_WRITE_REGISTER_L(dev->aal5.rx_max_sdu,AAL5_RMFL_ADDR);
2282 if (mem_addr != NULL) free_pages((unsigned long)mem_addr,get_log_2(((CBM_CELL_SIZE * dev->cbm.free_cell_cnt) >>PAGE_SHIFT) + 1));
2511 int amazon_atm_ioctl(struct atm_dev *dev,unsigned int cmd,void *arg)
2651 vcc->itf = (int) vcc->dev->dev_data;
3011 amazon_atm_dev_t *dev = NULL;
3013 if ((dev=amazon_atm_create()) != NULL){
3015 if (!dev->ports[i].enable){
3028 amazon_atm_devs[i]->link_rate = dev->ports[i].tx_max_cr;
3056 AMAZON_TPE_DMSG("unregister dev %u\n",i);