Lines Matching refs:gmacdev
47 int32_t nss_gmac_check_link(struct nss_gmac_dev *gmacdev)
49 struct phy_device *phydev = gmacdev->phydev;
51 if (!test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags))
55 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII
56 || gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII) {
171 uint16_t nss_gmac_mii_rd_reg(struct nss_gmac_dev *gmacdev, uint32_t phy,
176 if (IS_ERR(gmacdev->phydev)) {
177 netdev_dbg(gmacdev->netdev, "Error: Reading uninitialized PHY...\n");
181 data = (uint16_t)phy_read(gmacdev->phydev, reg);
195 void nss_gmac_mii_wr_reg(struct nss_gmac_dev *gmacdev, uint32_t phy,
198 if (IS_ERR(gmacdev->phydev))
199 netdev_dbg(gmacdev->netdev, "Error: Writing uninitialized PHY...\n");
201 phy_write(gmacdev->phydev, reg, data);
210 void nss_gmac_reset_phy(struct nss_gmac_dev *gmacdev, uint32_t phyid)
213 if (gmacdev->phy_mii_type != PHY_INTERFACE_MODE_RGMII)
217 nss_gmac_mii_wr_reg(gmacdev, phyid, MII_BMCR, BMCR_RESET);
218 nss_gmac_mii_wr_reg(gmacdev, phyid, MII_BMCR,
219 nss_gmac_mii_rd_reg(gmacdev, phyid, MII_BMCR)
222 set_bit(__NSS_GMAC_AUTONEG, &gmacdev->flags);
223 netdev_dbg(gmacdev->netdev, "Phy %u reset OK\n", phyid);
233 int32_t nss_gmac_read_version(struct nss_gmac_dev *gmacdev)
237 data = nss_gmac_read_reg(gmacdev->mac_base, gmac_version);
238 gmacdev->version = data;
249 void nss_gmac_reset(struct nss_gmac_dev *gmacdev)
256 netdev = gmacdev->netdev;
257 ctx = gmacdev->ctx;
263 nss_gmac_write_reg(gmacdev->dma_base, dma_bus_mode, dma_reset_on);
267 nss_gmac_read_reg(gmacdev->dma_base, dma_bus_mode);
271 data = nss_gmac_read_reg(gmacdev->dma_base, dma_bus_mode);
285 int32_t nss_gmac_dma_bus_mode_init(struct nss_gmac_dev *gmacdev,
288 nss_gmac_write_reg(gmacdev->dma_base, dma_bus_mode, init_value);
301 int32_t nss_gmac_dma_axi_bus_mode_init(struct nss_gmac_dev *gmacdev,
304 nss_gmac_write_reg(gmacdev->dma_base, dma_axi_bus_mode, init_value);
317 int32_t nss_gmac_dma_control_init(struct nss_gmac_dev *gmacdev,
320 nss_gmac_write_reg(gmacdev->dma_base, dma_control, init_value);
333 void nss_gmac_wd_enable(struct nss_gmac_dev *gmacdev)
335 nss_gmac_clear_reg_bits(gmacdev->mac_base,
346 void nss_gmac_jab_enable(struct nss_gmac_dev *gmacdev)
348 nss_gmac_set_reg_bits(gmacdev->mac_base,
359 void nss_gmac_frame_burst_enable(struct nss_gmac_dev *gmacdev)
361 nss_gmac_set_reg_bits(gmacdev->mac_base,
372 void nss_gmac_jumbo_frame_enable(struct nss_gmac_dev *gmacdev)
374 nss_gmac_set_reg_bits(gmacdev->mac_base,
385 void nss_gmac_jumbo_frame_disable(struct nss_gmac_dev *gmacdev)
387 nss_gmac_clear_reg_bits(gmacdev->mac_base,
398 void nss_gmac_twokpe_frame_enable(struct nss_gmac_dev *gmacdev)
400 nss_gmac_set_reg_bits(gmacdev->mac_base,
411 void nss_gmac_twokpe_frame_disable(struct nss_gmac_dev *gmacdev)
413 nss_gmac_clear_reg_bits(gmacdev->mac_base,
424 void nss_gmac_disable_crs(struct nss_gmac_dev *gmacdev)
426 nss_gmac_set_reg_bits(gmacdev->mac_base,
437 void nss_gmac_enable_crs(struct nss_gmac_dev *gmacdev)
439 nss_gmac_clear_reg_bits(gmacdev->mac_base,
450 void nss_gmac_select_gmii(struct nss_gmac_dev *gmacdev)
452 nss_gmac_clear_reg_bits(gmacdev->mac_base,
463 void nss_gmac_select_mii(struct nss_gmac_dev *gmacdev)
465 nss_gmac_set_reg_bits(gmacdev->mac_base,
468 if (gmacdev->speed == SPEED_100) {
469 nss_gmac_set_reg_bits(gmacdev->mac_base,
474 nss_gmac_clear_reg_bits(gmacdev->mac_base,
484 void nss_gmac_rx_own_enable(struct nss_gmac_dev *gmacdev)
486 nss_gmac_clear_reg_bits(gmacdev->mac_base,
497 void nss_gmac_rx_own_disable(struct nss_gmac_dev *gmacdev)
499 nss_gmac_set_reg_bits(gmacdev->mac_base,
508 void nss_gmac_loopback_off(struct nss_gmac_dev *gmacdev)
510 nss_gmac_clear_reg_bits(gmacdev->mac_base,
519 void nss_gmac_set_full_duplex(struct nss_gmac_dev *gmacdev)
521 nss_gmac_set_reg_bits(gmacdev->mac_base,
530 void nss_gmac_set_half_duplex(struct nss_gmac_dev *gmacdev)
532 nss_gmac_clear_reg_bits(gmacdev->mac_base,
545 void nss_gmac_retry_enable(struct nss_gmac_dev *gmacdev)
547 nss_gmac_clear_reg_bits(gmacdev->mac_base,
559 void nss_gmac_retry_disable(struct nss_gmac_dev *gmacdev)
561 nss_gmac_set_reg_bits(gmacdev->mac_base,
571 void nss_gmac_pad_crc_strip_disable(struct nss_gmac_dev *gmacdev)
573 nss_gmac_clear_reg_bits(gmacdev->mac_base,
582 * nss_gmac_retry_enable(nss_gmac_dev *gmacdev)
584 void nss_gmac_back_off_limit(struct nss_gmac_dev *gmacdev, uint32_t value)
588 data = nss_gmac_read_reg(gmacdev->mac_base, gmac_config);
591 nss_gmac_write_reg(gmacdev->mac_base, gmac_config, data);
600 void nss_gmac_deferral_check_disable(struct nss_gmac_dev *gmacdev)
602 nss_gmac_clear_reg_bits(gmacdev->mac_base,
611 void nss_gmac_rx_enable(struct nss_gmac_dev *gmacdev)
613 nss_gmac_set_reg_bits(gmacdev->mac_base, gmac_config,
624 void nss_gmac_rx_disable(struct nss_gmac_dev *gmacdev)
626 nss_gmac_clear_reg_bits(gmacdev->mac_base,
636 void nss_gmac_tx_enable(struct nss_gmac_dev *gmacdev)
638 nss_gmac_set_reg_bits(gmacdev->mac_base, gmac_config,
649 void nss_gmac_tx_disable(struct nss_gmac_dev *gmacdev)
651 nss_gmac_clear_reg_bits(gmacdev->mac_base,
664 void nss_gmac_frame_filter_enable(struct nss_gmac_dev *gmacdev)
666 nss_gmac_clear_reg_bits(gmacdev->mac_base,
677 void nss_gmac_src_addr_filter_disable(struct nss_gmac_dev *gmacdev)
679 nss_gmac_clear_reg_bits(gmacdev->mac_base,
688 void nss_gmac_dst_addr_filter_normal(struct nss_gmac_dev *gmacdev)
690 nss_gmac_clear_reg_bits(gmacdev->mac_base,
703 void nss_gmac_set_pass_control(struct nss_gmac_dev *gmacdev,
709 nss_gmac_read_reg(gmacdev->mac_base, gmac_frame_filter);
712 nss_gmac_write_reg(gmacdev->mac_base, gmac_frame_filter,
722 void nss_gmac_broadcast_enable(struct nss_gmac_dev *gmacdev)
724 nss_gmac_clear_reg_bits(gmacdev->mac_base,
734 void nss_gmac_multicast_enable(struct nss_gmac_dev *gmacdev)
736 nss_gmac_set_reg_bits(gmacdev->mac_base,
746 void nss_gmac_multicast_disable(struct nss_gmac_dev *gmacdev)
748 nss_gmac_clear_reg_bits(gmacdev->mac_base,
760 void nss_gmac_multicast_hash_filter_disable(struct nss_gmac_dev *gmacdev)
762 nss_gmac_clear_reg_bits(gmacdev->mac_base,
773 void nss_gmac_promisc_enable(struct nss_gmac_dev *gmacdev)
775 nss_gmac_set_reg_bits(gmacdev->mac_base,
785 void nss_gmac_promisc_disable(struct nss_gmac_dev *gmacdev)
787 nss_gmac_clear_reg_bits(gmacdev->mac_base,
798 void nss_gmac_unicast_hash_filter_disable(struct nss_gmac_dev *gmacdev)
800 nss_gmac_clear_reg_bits(gmacdev->mac_base,
812 void nss_gmac_unicast_pause_frame_detect_disable(struct nss_gmac_dev *gmacdev)
814 nss_gmac_clear_reg_bits(gmacdev->mac_base,
824 void nss_gmac_rx_flow_control_disable(struct nss_gmac_dev *gmacdev)
826 nss_gmac_clear_reg_bits(gmacdev->mac_base,
838 void nss_gmac_tx_flow_control_disable(struct nss_gmac_dev *gmacdev)
840 nss_gmac_clear_reg_bits(gmacdev->mac_base,
850 void nss_gmac_tx_pause_enable(struct nss_gmac_dev *gmacdev)
852 netdev_dbg(gmacdev->netdev, "%s: enable Tx flow control\n", __func__);
854 nss_gmac_set_reg_bits(gmacdev->mac_base,
863 void nss_gmac_tx_pause_disable(struct nss_gmac_dev *gmacdev)
865 netdev_dbg(gmacdev->netdev, "%s: disable Tx flow control\n", __func__);
867 nss_gmac_clear_reg_bits(gmacdev->mac_base,
878 void nss_gmac_rx_pause_enable(struct nss_gmac_dev *gmacdev)
880 netdev_dbg(gmacdev->netdev, "%s: enable Rx flow control\n", __func__);
882 nss_gmac_clear_reg_bits(gmacdev->dma_base, dma_control,
886 nss_gmac_set_reg_bits(gmacdev->mac_base,
895 void nss_gmac_rx_pause_disable(struct nss_gmac_dev *gmacdev)
897 netdev_dbg(gmacdev->netdev, "%s: disable Rx flow control\n", __func__);
899 nss_gmac_clear_reg_bits(gmacdev->dma_base,dma_control,
902 nss_gmac_clear_reg_bits(gmacdev->mac_base,
912 void nss_gmac_flush_tx_fifo(struct nss_gmac_dev *gmacdev)
914 nss_gmac_set_reg_bits(gmacdev->dma_base, dma_control,
923 void nss_gmac_config_flow_control(struct nss_gmac_dev *gmacdev)
927 netdev_dbg(gmacdev->netdev, "%s:\n", __func__);
929 if (gmacdev->pause == 0) {
930 nss_gmac_rx_pause_disable(gmacdev);
931 nss_gmac_tx_pause_disable(gmacdev);
935 phyreg = nss_gmac_mii_rd_reg(gmacdev, gmacdev->phy_base, MII_LPA);
939 netdev_dbg(gmacdev->netdev,
943 if (gmacdev->pause & FLOW_CTRL_RX)
944 nss_gmac_rx_pause_enable(gmacdev);
946 if (gmacdev->pause & FLOW_CTRL_TX)
947 nss_gmac_tx_pause_enable(gmacdev);
954 netdev_dbg(gmacdev->netdev,
961 nss_gmac_rx_pause_disable(gmacdev);
962 if (gmacdev->pause & FLOW_CTRL_TX)
963 nss_gmac_tx_pause_enable(gmacdev);
969 netdev_dbg(gmacdev->netdev,
972 nss_gmac_rx_flow_control_disable(gmacdev);
973 nss_gmac_tx_flow_control_disable(gmacdev);
981 void nss_gmac_ipc_offload_init(struct nss_gmac_dev *gmacdev)
983 if (test_bit(__NSS_GMAC_RXCSUM, &gmacdev->flags)) {
985 nss_gmac_enable_rx_chksum_offload(gmacdev);
990 nss_gmac_rx_tcpip_chksum_drop_enable(gmacdev);
991 netdev_dbg(gmacdev->netdev, "%s: enable Rx checksum\n", __func__);
993 nss_gmac_disable_rx_chksum_offload(gmacdev);
994 netdev_dbg(gmacdev->netdev, "%s: disable Rx checksum\n", __func__);
1006 void nss_gmac_mac_init(struct nss_gmac_dev *gmacdev)
1008 nss_gmac_wd_enable(gmacdev);
1009 nss_gmac_jab_enable(gmacdev);
1010 nss_gmac_frame_burst_enable(gmacdev);
1011 nss_gmac_loopback_off(gmacdev);
1013 if (gmacdev->speed == SPEED_1000)
1014 nss_gmac_select_gmii(gmacdev);
1016 nss_gmac_select_mii(gmacdev);
1018 if (gmacdev->duplex_mode == DUPLEX_FULL) {
1019 nss_gmac_set_full_duplex(gmacdev);
1020 nss_gmac_rx_own_enable(gmacdev);
1021 nss_gmac_retry_disable(gmacdev);
1022 nss_gmac_enable_crs(gmacdev);
1024 nss_gmac_set_half_duplex(gmacdev);
1025 nss_gmac_rx_own_disable(gmacdev);
1026 nss_gmac_retry_enable(gmacdev);
1027 nss_gmac_disable_crs(gmacdev);
1030 nss_gmac_pad_crc_strip_disable(gmacdev);
1031 nss_gmac_back_off_limit(gmacdev, gmac_backoff_limit0);
1032 nss_gmac_deferral_check_disable(gmacdev);
1034 nss_gmac_set_mac_addr(gmacdev, gmac_addr0_high,
1035 gmac_addr0_low, gmacdev->netdev->dev_addr);
1038 nss_gmac_frame_filter_enable(gmacdev);
1039 nss_gmac_set_pass_control(gmacdev, gmac_pass_control0);
1040 nss_gmac_broadcast_enable(gmacdev);
1041 nss_gmac_src_addr_filter_disable(gmacdev);
1042 nss_gmac_multicast_enable(gmacdev);
1043 gmacdev->netdev->flags |= IFF_ALLMULTI;
1044 nss_gmac_dst_addr_filter_normal(gmacdev);
1045 nss_gmac_multicast_hash_filter_disable(gmacdev);
1046 nss_gmac_promisc_enable(gmacdev);
1047 nss_gmac_unicast_hash_filter_disable(gmacdev);
1049 nss_gmac_ipc_offload_init(gmacdev);
1052 nss_gmac_unicast_pause_frame_detect_disable(gmacdev);
1053 nss_gmac_config_flow_control(gmacdev);
1055 nss_gmac_tx_enable(gmacdev);
1056 nss_gmac_rx_enable(gmacdev);
1060 static void nss_gmac_check_pcs_status(struct nss_gmac_dev *gmacdev)
1067 ctx = gmacdev->ctx;
1069 id = gmacdev->sgmii_pcs_chanid;
1071 gmacdev->link_state = LINKDOWN;
1078 gmacdev->link_state = LINKUP;
1082 gmacdev->duplex_mode = DUPLEX_FULL;
1084 gmacdev->duplex_mode = DUPLEX_HALF;
1089 gmacdev->speed = SPEED_10;
1093 gmacdev->speed = SPEED_100;
1097 gmacdev->speed = SPEED_1000;
1108 static void nss_gmac_check_sgmii_link(struct nss_gmac_dev *gmacdev)
1121 ctx = gmacdev->ctx;
1123 id = gmacdev->sgmii_pcs_chanid;
1125 previous_linkup_speed = gmacdev->speed;
1126 previous_linkup_duplex = gmacdev->duplex_mode;
1129 nss_gmac_check_pcs_status(gmacdev);
1130 if (gmacdev->link_state == LINKDOWN) {
1131 if (gmacdev->phydev->link) {
1132 netdev_dbg(gmacdev->netdev, "SGMII PCS error. Resetting PHY using MDIO\n");
1133 phy_write(gmacdev->phydev, MII_BMCR,
1134 BMCR_RESET | phy_read(gmacdev->phydev, MII_BMCR));
1140 new_speed = gmacdev->speed;
1141 new_duplex = gmacdev->duplex_mode;
1158 netdev_dbg(gmacdev->netdev, "%s: PCS ch %d autoneg timeout\n",
1162 gmacdev->link_state = LINKDOWN;
1169 netdev_dbg(gmacdev->netdev, "%s: PCS ch %d autoneg complete\n",
1172 nss_gmac_check_pcs_status(gmacdev);
1174 if ((gmacdev->link_state == LINKDOWN) || (new_speed != gmacdev->speed)) {
1175 gmacdev->link_state = LINKDOWN;
1176 netdev_dbg(gmacdev->netdev, "SGMII PCS error. Resetting PHY using MDIO\n");
1177 phy_write(gmacdev->phydev, MII_BMCR,
1178 BMCR_RESET | phy_read(gmacdev->phydev, MII_BMCR));
1183 if (previous_linkup_speed != gmacdev->speed) {
1185 nss_gmac_dev_set_speed(gmacdev);
1188 nss_gmac_flush_tx_fifo(gmacdev);
1197 * @return 0 on success. If successful, it updates gmacdev->speed and
1198 * gmacdev->duplex_mode with current speed and duplex mode.
1200 int32_t nss_gmac_check_phy_init(struct nss_gmac_dev *gmacdev)
1209 if (!test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)
1210 && (gmacdev->forced_speed == SPEED_UNKNOWN)) {
1211 netdev_dbg(gmacdev->netdev,
1221 if (test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) {
1222 phydev = gmacdev->phydev;
1223 if (gmacdev->phydev->is_c45 == false) {
1235 if (gmacdev->forced_speed != SPEED_UNKNOWN) {
1239 gmacdev->speed = gmacdev->forced_speed;
1240 gmacdev->duplex_mode = gmacdev->forced_duplex;
1250 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII
1251 || gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII) {
1252 nss_gmac_check_sgmii_link(gmacdev);
1253 if (gmacdev->link_state == LINKDOWN) {
1254 netdev_dbg(gmacdev->netdev, "%s: SGMII phy linkup ERROR.\n"
1259 netdev_dbg(gmacdev->netdev, "%s: SGMII phy linkup OK.\n",
1268 gmacdev->speed = phydev->speed;
1269 gmacdev->duplex_mode = phydev->duplex;
1277 if (test_bit(__NSS_GMAC_LINKPOLL, &gmacdev->flags)) {
1281 phy_link_speed = gmacdev->speed;
1282 phy_link_duplex = gmacdev->duplex_mode;
1285 netdev_info(gmacdev->netdev,
1386 void nss_gmac_set_mac_addr(struct nss_gmac_dev *gmacdev, uint32_t mac_high,
1391 netdev_dbg(gmacdev->netdev, "Set addr %02x:%02x:%02x:%02x:%02x:%02x\n",
1396 nss_gmac_write_reg(gmacdev->mac_base, mac_high, data);
1399 nss_gmac_write_reg(gmacdev->mac_base, mac_low, data);
1411 void nss_gmac_get_mac_addr(struct nss_gmac_dev *gmacdev, uint32_t mac_high,
1416 data = nss_gmac_read_reg(gmacdev->mac_base, mac_high);
1420 data = nss_gmac_read_reg(gmacdev->mac_base, mac_low);
1436 int32_t nss_gmac_attach(struct nss_gmac_dev *gmacdev,
1440 netdev = gmacdev->netdev;
1443 gmacdev->memres = request_mem_region(reg_base, reglen, netdev->name);
1444 if (!gmacdev->memres) {
1450 gmacdev->mac_base = ioremap_nocache(reg_base,
1452 if (!gmacdev->mac_base) {
1458 NSS_GMAC_REG_BLOCK_LEN, reg_base, gmacdev->mac_base);
1460 gmacdev->dma_base = gmacdev->mac_base + NSS_GMAC_DMABASE;
1472 void nss_gmac_detach(struct nss_gmac_dev *gmacdev)
1476 reglen = gmacdev->memres->end - gmacdev->memres->start + 1;
1477 iounmap((void *)gmacdev->mac_base);
1478 release_mem_region((gmacdev->memres)->start, reglen);
1480 gmacdev->memres = NULL;
1482 gmacdev->mac_base = 0;
1483 gmacdev->dma_base = 0;
1489 * Rx Descriptor's base address is available in the gmacdev structure.
1495 void nss_gmac_init_rx_desc_base(struct nss_gmac_dev *gmacdev)
1497 nss_gmac_write_reg(gmacdev->dma_base, dma_rx_base_addr,
1498 (uint32_t)gmacdev->rx_desc_dma);
1503 * Tx Descriptor's base address is available in the gmacdev structure.
1509 void nss_gmac_init_tx_desc_base(struct nss_gmac_dev *gmacdev)
1511 nss_gmac_write_reg(gmacdev->dma_base, dma_tx_base_addr,
1512 (uint32_t)gmacdev->tx_desc_dma);
1732 void nss_gmac_enable_dma_rx(struct nss_gmac_dev *gmacdev)
1736 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1738 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1746 void nss_gmac_enable_dma_tx(struct nss_gmac_dev *gmacdev)
1750 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1752 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1781 void nss_gmac_take_desc_ownership_rx(struct nss_gmac_dev *gmacdev)
1786 desc = gmacdev->rx_desc;
1787 for (i = 0; i < gmacdev->rx_desc_count; i++)
1802 void nss_gmac_take_desc_ownership_tx(struct nss_gmac_dev *gmacdev)
1807 desc = gmacdev->tx_desc;
1808 for (i = 0; i < gmacdev->tx_desc_count; i++)
1817 void nss_gmac_disable_dma_tx(struct nss_gmac_dev *gmacdev)
1821 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1823 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1831 void nss_gmac_disable_dma_rx(struct nss_gmac_dev *gmacdev)
1835 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1837 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1849 void nss_gmac_disable_mmc_tx_interrupt(struct nss_gmac_dev *gmacdev,
1852 nss_gmac_set_reg_bits(gmacdev->mac_base,
1863 void nss_gmac_disable_mmc_rx_interrupt(struct nss_gmac_dev *gmacdev,
1866 nss_gmac_set_reg_bits(gmacdev->mac_base,
1878 void nss_gmac_disable_mmc_ipc_rx_interrupt(struct nss_gmac_dev *gmacdev,
1881 nss_gmac_set_reg_bits(gmacdev->mac_base,
1896 void nss_gmac_enable_rx_chksum_offload(struct nss_gmac_dev *gmacdev)
1898 nss_gmac_set_reg_bits(gmacdev->mac_base,
1908 void nss_gmac_disable_rx_chksum_offload(struct nss_gmac_dev *gmacdev)
1910 nss_gmac_clear_reg_bits(gmacdev->mac_base,
1922 void nss_gmac_rx_tcpip_chksum_drop_enable(struct nss_gmac_dev *gmacdev)
1924 nss_gmac_clear_reg_bits(gmacdev->dma_base,
1936 void nss_gmac_rx_tcpip_chksum_drop_disable(struct nss_gmac_dev *gmacdev)
1938 nss_gmac_set_reg_bits(gmacdev->dma_base,