Lines Matching refs:gmacdev
57 void nss_gmac_spare_ctl(struct nss_gmac_dev *gmacdev)
61 uint32_t id = gmacdev->macid;
62 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
68 netdev_dbg(gmacdev->netdev, "NSS_ETH_SPARE_CTL - 0x%x\n", val);
74 netdev_dbg(gmacdev->netdev,
79 netdev_dbg(gmacdev->netdev,
88 netdev_dbg(gmacdev->netdev,
102 static void nss_gmac_rumi_qsgmii_init(struct nss_gmac_dev *gmacdev)
109 netdev_dbg(gmacdev->netdev, "%s:\n", __func__);
111 gmac1_dev = gmacdev->ctx->nss_gmac[1];
112 qsgmii_base = gmacdev->ctx->qsgmii_base;
113 nss_base = (uint8_t *)(gmacdev->ctx->nss_base);
119 netdev_dbg(gmacdev->netdev, "Eth2: spare_ctl_reg value before setting = 0x%x\n",
122 netdev_dbg(gmacdev->netdev, "Eth2: spare_ctl_reg value after setting = 0x%x\n",
155 netdev_dbg(gmacdev->netdev, "Reg 1A reset val: 0x%x\n", phy_reg_val);
163 netdev_dbg(gmacdev->netdev, "Reg 1A after programming: 0x%x\n",
181 void nss_gmac_qsgmii_dev_init(struct nss_gmac_dev *gmacdev)
184 uint32_t id = gmacdev->macid;
185 uint8_t *nss_base = (uint8_t *)(gmacdev->ctx->nss_base);
186 uint32_t *qsgmii_base = (uint32_t *)(gmacdev->ctx->qsgmii_base);
190 nss_gmac_rumi_qsgmii_init(gmacdev);
192 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII) {
193 switch (gmacdev->macid) {
195 if (SOCINFO_VERSION_MAJOR(gmacdev->ctx->socver) < 2) {
219 netdev_dbg(gmacdev->netdev, "%s: QSGMII_PHY_QSGMII_CTL(0x%x) - 0x%x\n",
239 netdev_dbg(gmacdev->netdev, "%s: QSGMII_PHY_SGMII_1_CTL(0x%x) - 0x%x\n",
258 netdev_dbg(gmacdev->netdev, "%s: QSGMII_PHY_SGMII_2_CTL(0x%x) - 0x%x\n",
266 if ((gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII)
267 || (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII)) {
274 netdev_dbg(gmacdev->netdev, "%s: NSS_QSGMII_CLK_CTL(0x%x) - 0x%x\n",
281 if (gmacdev->forced_speed == SPEED_UNKNOWN) {
283 PCS_CHn_SPEED_MASK(gmacdev->macid));
285 PCS_CHn_FORCE_SPEED(gmacdev->macid));
530 static uint32_t clk_div_qsgmii(struct nss_gmac_dev *gmacdev)
534 switch (gmacdev->speed) {
560 static uint32_t clk_div_sgmii(struct nss_gmac_dev *gmacdev)
564 switch (gmacdev->speed) {
590 static uint32_t clk_div_rgmii(struct nss_gmac_dev *gmacdev)
594 switch (gmacdev->speed) {
620 static uint32_t get_pcs_speed(struct nss_gmac_dev *gmacdev)
624 switch (gmacdev->speed) {
649 int32_t nss_gmac_dev_set_speed(struct nss_gmac_dev *gmacdev)
652 uint32_t id = gmacdev->macid;
655 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
656 uint32_t *qsgmii_base = (uint32_t *)(gmacdev->ctx->qsgmii_base);
660 switch (gmacdev->phy_mii_type) {
662 div = clk_div_rgmii(gmacdev);
666 div = clk_div_sgmii(gmacdev);
670 div = clk_div_qsgmii(gmacdev);
674 netdev_dbg(gmacdev->netdev, "%s: Invalid MII type\n", __func__);
678 if (gmacdev->forced_speed != SPEED_UNKNOWN)
684 if (((gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII) ||
685 (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII))
687 pcs_speed = get_pcs_speed(gmacdev);
698 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_RGMII)
714 netdev_dbg(gmacdev->netdev, "%s:NSS_ETH_CLK_DIV0(0x%x) - 0x%x\n",
717 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII
718 || gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII) {
732 netdev_dbg(gmacdev->netdev, "%s: qsgmii_base(0x%x) + PCS_MODE_CTL(0x%x): 0x%x\n",
738 gmac_speed_ctx.mac_id = gmacdev->macid;
739 gmac_speed_ctx.speed = gmacdev->speed;
751 void nss_gmac_dev_init(struct nss_gmac_dev *gmacdev)
755 uint32_t id = gmacdev->macid;
756 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
757 struct nss_gmac_global_ctx *ctx = gmacdev->ctx;
766 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_FS(%d)(0x%x): 0x%x\n",
781 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC_CTL(%d)(0x%x): 0x%x\n",
794 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC0_MD(%d)(0x%x): 0x%x\n",
798 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC1_MD(%d)(0x%x): 0x%x\n",
819 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC0_NS(%d)(0x%x): 0x%x\n",
823 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC1_NS(%d)(0x%x): 0x%x\n",
832 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + CLK_HALT_NSSFAB0_NSSFAB1_STATEA(0x%x): 0x%x\n",
842 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_CTL(%d)(0x%x): 0x%x\n",
850 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_RGMII)
859 netdev_dbg(gmacdev->netdev, "%s: nss_base(0x%x) + NSS_GMACn_CTL(%d)(0x%x): 0x%x\n",
874 gmacdev->speed = SPEED_1000;
875 switch (gmacdev->phy_mii_type) {
877 div = clk_div_rgmii(gmacdev);
881 div = clk_div_sgmii(gmacdev);
885 div = clk_div_qsgmii(gmacdev);
894 netdev_dbg(gmacdev->netdev, "%s: nss_base(0x%x) + NSS_ETH_CLK_DIV0(0x%x): 0x%x\n",
900 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_RGMII)
903 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII)
910 if (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_RGMII)
921 if ((gmacdev->phy_mii_type == PHY_INTERFACE_MODE_SGMII)
922 || (gmacdev->phy_mii_type == PHY_INTERFACE_MODE_QSGMII)) {
923 nss_gmac_qsgmii_dev_init(gmacdev);
924 netdev_dbg(gmacdev->netdev, "SGMII Specific Init for GMAC%d Done!\n", id);