Lines Matching refs:ctx
62 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
111 gmac1_dev = gmacdev->ctx->nss_gmac[1];
112 qsgmii_base = gmacdev->ctx->qsgmii_base;
113 nss_base = (uint8_t *)(gmacdev->ctx->nss_base);
185 uint8_t *nss_base = (uint8_t *)(gmacdev->ctx->nss_base);
186 uint32_t *qsgmii_base = (uint32_t *)(gmacdev->ctx->qsgmii_base);
195 if (SOCINFO_VERSION_MAJOR(gmacdev->ctx->socver) < 2) {
340 static void nss_gmac_qsgmii_common_init(struct nss_gmac_global_ctx *ctx)
343 uint32_t *qsgmii_base = ctx->qsgmii_base;
403 nss_gmac_write_reg((uint32_t *)(ctx->clk_ctl_base),
406 nss_gmac_write_reg((uint32_t *)(ctx->clk_ctl_base),
409 val = nss_gmac_read_reg((uint32_t *)(ctx->clk_ctl_base),
412 __func__, (uint32_t)(ctx->clk_ctl_base),
441 int32_t nss_gmac_common_init(struct nss_gmac_global_ctx *ctx)
445 nss_gmac_clear_all_regs((uint32_t *)ctx->nss_base);
447 nss_gmac_write_reg((uint32_t *)(ctx->qsgmii_base),
456 nss_gmac_write_reg((uint32_t *)(ctx->qsgmii_base), PCS_CAL_LCKDT_CTL,
468 nss_gmac_clear_reg_bits((uint32_t *)(ctx->clk_ctl_base),
470 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_AHB_RESET);
471 pr_debug("%s: ctx->clk_ctl_base(0x%x) + GMAC_AHB_RESET(0x%x): 0x%x\n",
472 __func__, (uint32_t)ctx->clk_ctl_base,
476 nss_gmac_set_reg_bits((uint32_t *)(ctx->nss_base), NSS_MACSEC_CTL,
480 val = nss_gmac_read_reg((uint32_t *)ctx->nss_base, NSS_MACSEC_CTL);
482 __func__, (uint32_t)ctx->nss_base,
485 nss_gmac_qsgmii_common_init(ctx);
491 nss_gmac_clear_reg_bits((uint32_t *)(ctx->clk_ctl_base), NSS_ACC_REG,
493 val = nss_gmac_read_reg(ctx->clk_ctl_base, NSS_ACC_REG);
494 pr_debug("%s: ctx->clk_ctl_base(0x%x) + NSS_ACC_REG(0x%x): 0x%x\n",
495 __func__, (uint32_t)ctx->clk_ctl_base,
505 void nss_gmac_common_deinit(struct nss_gmac_global_ctx *ctx)
507 nss_gmac_clear_all_regs((uint32_t *)ctx->nss_base);
509 if (ctx->qsgmii_base) {
510 iounmap(ctx->qsgmii_base);
511 ctx->qsgmii_base = NULL;
514 if (ctx->clk_ctl_base) {
515 iounmap(ctx->clk_ctl_base);
516 ctx->clk_ctl_base = NULL;
519 if (ctx->nss_base) {
520 iounmap(ctx->nss_base);
521 ctx->nss_base = NULL;
655 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
656 uint32_t *qsgmii_base = (uint32_t *)(gmacdev->ctx->qsgmii_base);
756 uint32_t *nss_base = (uint32_t *)(gmacdev->ctx->nss_base);
757 struct nss_gmac_global_ctx *ctx = gmacdev->ctx;
763 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_FS(id),
765 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_FS(id));
766 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_FS(%d)(0x%x): 0x%x\n",
767 __func__, (uint32_t)ctx->clk_ctl_base, id, (uint32_t)GMAC_COREn_CLK_FS(id), val);
773 nss_gmac_clear_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC_CTL(id),
777 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC_CTL(id),
780 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC_CTL(id));
781 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC_CTL(%d)(0x%x): 0x%x\n",
782 __func__, (uint32_t)ctx->clk_ctl_base, id,
786 nss_gmac_write_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_MD(id), 0);
787 nss_gmac_write_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_MD(id), 0);
788 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_MD(id),
790 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_MD(id),
793 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_MD(id));
794 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC0_MD(%d)(0x%x): 0x%x\n",
795 __func__, (uint32_t)ctx->clk_ctl_base, id,
797 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_MD(id));
798 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC1_MD(%d)(0x%x): 0x%x\n",
799 __func__, (uint32_t)ctx->clk_ctl_base, id,
803 nss_gmac_write_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_NS(id), 0);
804 nss_gmac_write_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_NS(id), 0);
805 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_NS(id),
811 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_NS(id),
818 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC0_NS(id));
819 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC0_NS(%d)(0x%x): 0x%x\n",
820 __func__, (uint32_t)ctx->clk_ctl_base, id,
822 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_SRC1_NS(id));
823 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_SRC1_NS(%d)(0x%x): 0x%x\n",
824 __func__, (uint32_t)ctx->clk_ctl_base, id,
828 nss_gmac_clear_reg_bits(ctx->clk_ctl_base,
830 val = nss_gmac_read_reg(ctx->clk_ctl_base,
832 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + CLK_HALT_NSSFAB0_NSSFAB1_STATEA(0x%x): 0x%x\n",
833 __func__, (uint32_t)ctx->clk_ctl_base,
837 nss_gmac_clear_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_CTL(id),
839 nss_gmac_set_reg_bits(ctx->clk_ctl_base, GMAC_COREn_CLK_CTL(id),
841 val = nss_gmac_read_reg(ctx->clk_ctl_base, GMAC_COREn_CLK_CTL(id));
842 netdev_dbg(gmacdev->netdev, "%s: ctx->clk_ctl_base(0x%x) + GMAC_COREn_CLK_CTL(%d)(0x%x): 0x%x\n",
843 __func__, (uint32_t)ctx->clk_ctl_base, id,
871 nss_gmac_clear_reg_bits(ctx->clk_ctl_base, GMAC_COREn_RESET(id), 0x1);
935 uint32_t *nss_base = (uint32_t *)ctx.nss_base;
949 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE1_RESET, 1);
950 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE2_RESET, 1);
951 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE3_RESET, 1);
955 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE1_RESET, 0);
956 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE2_RESET, 0);
957 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE3_RESET, 0);
979 uint32_t *nss_base = (uint32_t *)ctx.nss_base;
997 gmac_dev = ctx.nss_gmac[gmac_id];
1019 uint32_t *nss_base = (uint32_t *)ctx.nss_base;
1027 gmac_dev = ctx.nss_gmac[gmac_id];
1082 uint32_t *nss_base = (uint32_t *)ctx.nss_base;
1088 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE1_RESET, 1);
1089 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE2_RESET, 1);
1090 nss_gmac_write_reg(ctx.clk_ctl_base, MACSEC_CORE3_RESET, 1);
1098 gmac_dev = ctx.nss_gmac[gmac_id];