Lines Matching defs:data
68 * is a slow process as the data is moved accross MDI/MDO interface
73 * @param[out] uint16_t data read from the respective phy register
79 uint32_t reg_offset, uint16_t *data,
93 /* write the address from where the data to be read in
103 *data =
113 pr_debug("Error::: PHY not responding; Busy bit not cleared!! addr:%x, data:%x\n",
114 temp, *data);
121 * is a slow process as the data is moved accross MDI/MDO interface
126 * @param[in] data to be written to the respective phy register.
131 uint32_t reg_offset, uint16_t data,
138 /* write the data in to gmac_gmii_data register of GMAC ip */
139 nss_gmac_write_reg(reg_base, gmac_gmii_data, data);
157 pr_debug("Error::: PHY not responding; Busy bit not cleared!! addr:data %x:%x\n",
158 temp, data);
174 uint16_t data = 0;
181 data = (uint16_t)phy_read(gmacdev->phydev, reg);
183 return data;
196 uint32_t reg, uint16_t data)
201 phy_write(gmacdev->phydev, reg, data);
229 * same in device data structure.
235 uint32_t data = 0;
237 data = nss_gmac_read_reg(gmacdev->mac_base, gmac_version);
238 gmacdev->version = data;
251 uint32_t data = 0;
266 data =
268 } while (data & dma_reset_on);
271 data = nss_gmac_read_reg(gmacdev->dma_base, dma_bus_mode);
273 netdev_dbg(netdev, "GMAC reset completed in %d jiffies; dma_bus_mode - 0x%x\n", (int)(jiffies - reset_time), data);
282 * @param[in] the data to be programmed.
298 * @param[in] the data to be programmed.
314 * @param[in] the data to be programmed.
329 * 2048 bytes of data (10,240 if Jumbo frame enabled).
586 uint32_t data;
588 data = nss_gmac_read_reg(gmacdev->mac_base, gmac_config);
589 data &= (~gmac_backoff_limit);
590 data |= value;
591 nss_gmac_write_reg(gmacdev->mac_base, gmac_config, data);
706 uint32_t data;
708 data =
710 data &= (~gmac_pass_control);
711 data |= passcontrol;
713 data);
1389 uint32_t data;
1395 data = (mac_addr[5] << 8) | mac_addr[4] | 0x80000000;
1396 nss_gmac_write_reg(gmacdev->mac_base, mac_high, data);
1397 data = (mac_addr[3] << 24) | (mac_addr[2] << 16)
1399 nss_gmac_write_reg(gmacdev->mac_base, mac_low, data);
1414 uint32_t data;
1416 data = nss_gmac_read_reg(gmacdev->mac_base, mac_high);
1417 mac_addr[5] = (data >> 8) & 0xff;
1418 mac_addr[4] = (data) & 0xff;
1420 data = nss_gmac_read_reg(gmacdev->mac_base, mac_low);
1421 mac_addr[3] = (data >> 24) & 0xff;
1422 mac_addr[2] = (data >> 16) & 0xff;
1423 mac_addr[1] = (data >> 8) & 0xff;
1424 mac_addr[0] = (data) & 0xff;
1551 * This function is to check whether the descriptor's data buffer
1563 * This function is to check whether the descriptor's data buffer
1734 uint32_t data;
1736 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1737 data |= dma_rx_start;
1738 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1748 uint32_t data;
1750 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1751 data |= dma_tx_start;
1752 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1819 uint32_t data;
1821 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1822 data &= (~dma_tx_start);
1823 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);
1833 uint32_t data;
1835 data = nss_gmac_read_reg(gmacdev->dma_base, dma_control);
1836 data &= (~dma_rx_start);
1837 nss_gmac_write_reg(gmacdev->dma_base, dma_control, data);