Lines Matching refs:sii
77 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,
79 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
80 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
83 static void si_nvram_process(si_info_t *sii, char *pvars);
91 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
92 static bool si_ispcie(si_info_t *sii);
93 static uint BCMINITFN(socram_banksize)(si_info_t *sii, sbsocramregs_t *r, uint8 idx, uint8 mtype);
141 si_info_t *sii;
144 if ((sii = MALLOC(osh, sizeof (si_info_t))) == NULL) {
149 if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
150 MFREE(osh, sii, sizeof(si_info_t));
153 sii->vars = vars ? *vars : NULL;
154 sii->varsz = varsz ? *varsz : 0;
156 return (si_t *)sii;
213 si_info_t *sii = SI_INFO(sih);
217 rev_id = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_REV, sizeof(uint32));
230 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
231 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), SI_ENUM_BASE);
237 W_REG(sii->osh, PMUREG(sih, regcontrol_addr), 0);
238 /* AND_REG(sii->osh, PMUREG(sih, regcontrol_data), ~0x80); */
239 W_REG(sii->osh, PMUREG(sih, regcontrol_data), 0x3001);
244 W_REG(sii->osh, PMUREG(sih, min_res_mask), 0x0d);
246 SPINWAIT(((ccst = OSL_PCI_READ_CONFIG(sii->osh, PCI_CLK_CTL_ST, 4)) & CCS_ALPAVAIL)
255 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), w);
261 BCMATTACHFN(si_buscore_prep)(si_info_t *sii, uint bustype, uint devid, void *sdh)
265 sii->memseg = TRUE;
268 if (!si_ldo_war((si_t *)sii, devid))
273 if (BUSTYPE(bustype) == PCI_BUS && !si_ispcie(sii))
274 si_clkctl_xtal(&sii->pub, XTAL|PLL, ON);
281 BCMATTACHFN(si_buscore_setup)(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
289 if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
290 ai_enable_backplane_timeouts(&sii->pub);
292 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
296 sii->pub.ccrev = (int)si_corerev(&sii->pub);
299 if (sii->pub.ccrev >= 11)
300 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
303 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
306 if (sii->pub.ccrev >= 35)
307 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
310 if (sii->pub.cccaps & CC_CAP_PMU) {
311 if (AOB_ENAB(&sii->pub)) {
314 pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);
315 pmu = si_setcoreidx(&sii->pub, pmucoreidx);
316 sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);
317 si_setcoreidx(&sii->pub, SI_CC_IDX);
319 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
321 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
325 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
326 sii->pub.pmucaps));
329 sii->pub.buscoretype = NODEV_CORE_ID;
330 sii->pub.buscorerev = (uint)NOREV;
331 sii->pub.buscoreidx = BADIDX;
337 for (i = 0; i < sii->numcores; i++) {
340 si_setcoreidx(&sii->pub, i);
341 cid = si_coreid(&sii->pub);
342 crev = si_corerev(&sii->pub);
346 i, cid, crev, sii->coresba[i], sii->regs[i]));
374 sii->pub.buscorerev = crev;
375 sii->pub.buscoretype = cid;
376 sii->pub.buscoreidx = i;
380 if ((savewin && (savewin == sii->coresba[i])) ||
381 (regs == sii->regs[i]))
386 if (si_ispcie(sii))
395 sii->pub.buscoretype = PCI_CORE_ID;
396 sii->pub.buscorerev = pcirev;
397 sii->pub.buscoreidx = pciidx;
400 sii->pub.buscoretype = PCIE2_CORE_ID;
402 sii->pub.buscoretype = PCIE_CORE_ID;
403 sii->pub.buscorerev = pcierev;
404 sii->pub.buscoreidx = pcieidx;
407 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,
408 sii->pub.buscorerev));
410 if (BUSTYPE(sii->pub.bustype) == SI_BUS && (CHIPID(sii->pub.chip) == BCM4712_CHIP_ID) &&
411 (sii->pub.chippkg != BCM4712LARGE_PKG_ID) && (CHIPREV(sii->pub.chiprev) <= 3))
412 OR_REG(sii->osh, &cc->slow_clk_ctl, SCC_SS_XTAL);
415 if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
416 if (SI_FAST(sii)) {
417 if (!sii->pch &&
418 ((sii->pch = (void *)(uintptr)pcicore_init(&sii->pub, sii->osh,
419 (void *)PCIEREGS(sii))) == NULL))
422 if (si_pci_fixcfg(&sii->pub)) {
430 si_setcoreidx(&sii->pub, *origidx);
454 BCMATTACHFN(si_fixup_vid)(si_info_t *sii, char *pvars, uint32 conf_vid)
456 struct si_pub *sih = &sii->pub;
480 si_fixup_vid_overrides(si_info_t *sii, char *pvars, uint32 conf_vid)
482 if ((sii->pub.boardvendor != VENDOR_APPLE)) {
486 switch (sii->pub.boardtype)
493 sii->pub.boardtype = (conf_vid >> 16) & 0xffff;
504 BCMATTACHFN(si_nvram_process)(si_info_t *sii, char *pvars)
507 if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
509 sii->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
513 switch (BUSTYPE(sii->pub.bustype)) {
516 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32));
517 w = si_fixup_vid(sii, pvars, w);
520 if ((sii->pub.boardvendor = (uint16)si_getdevpathintvar(&sii->pub,
524 sii->pub.boardvendor = VENDOR_BROADCOM;
527 sii->pub.boardvendor = w & 0xffff;
531 sii->pub.boardvendor, w & 0xffff));
532 if ((sii->pub.boardtype = (uint16)si_getdevpathintvar(&sii->pub, rstr_boardtype))
534 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0)
535 sii->pub.boardtype = (w >> 16) & 0xffff;
539 sii->pub.boardtype, (w >> 16) & 0xffff));
542 si_fixup_vid_overrides(sii, pvars, w);
546 sii->pub.boardvendor = getintvar(pvars, rstr_manfid);
547 sii->pub.boardtype = getintvar(pvars, rstr_prodid);
553 sii->pub.boardvendor = VENDOR_BROADCOM;
554 if (pvars == NULL || ((sii->pub.boardtype = getintvar(pvars, rstr_prodid)) == 0))
555 if ((sii->pub.boardtype = getintvar(pvars, rstr_boardtype)) == 0)
556 sii->pub.boardtype = 0xffff;
558 if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
560 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32));
561 sii->pub.boardvendor = w & 0xffff;
562 sii->pub.boardtype = (w >> 16) & 0xffff;
567 if (sii->pub.boardtype == 0) {
569 ASSERT(sii->pub.boardtype);
572 sii->pub.boardrev = getintvar(pvars, rstr_boardrev);
573 sii->pub.boardflags = getintvar(pvars, rstr_boardflags);
575 sii->pub.boardflags2 |= ((!CHIP_HOSTIF_USB(&(sii->pub))) ? ((si_arm_sflags(&(sii->pub))
1197 si_info_t *sii;
1200 sii = SI_INFO(sih);
1204 sii = SI_INFO(sih);
1210 ASSERT(sii->gci_gpio_head != NULL);
1212 if ((void*)sii->gci_gpio_head == gci_i) {
1213 sii->gci_gpio_head = sii->gci_gpio_head->next;
1214 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t));
1217 p = sii->gci_gpio_head;
1222 MFREE(sii->osh, gci_i, sizeof(gci_gpio_item_t));
1235 si_info_t *sii;
1238 sii = SI_INFO(sih);
1242 sii = SI_INFO(sih);
1255 gci_i = MALLOC(sii->osh, (sizeof(gci_gpio_item_t)));
1263 if (sii->gci_gpio_head)
1264 gci_i->next = sii->gci_gpio_head;
1268 sii->gci_gpio_head = gci_i;
1281 si_info_t *sii;
1285 sii = SI_INFO(sih);
1298 gci_i = sii->gci_gpio_head;
1805 BCMATTACHFN(si_doattach)(si_info_t *sii, uint devid, osl_t *osh, void *regs,
1808 struct si_pub *sih = &sii->pub;
1819 bzero((uchar*)sii, sizeof(si_info_t));
1825 sii->curmap = regs;
1826 sii->sdh = sdh;
1827 sii->osh = osh;
1835 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) {
1843 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
1846 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
1862 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
1890 if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {
1892 sb_scan(&sii->pub, regs, devid);
1893 } else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) ||
1894 (CHIPTYPE(sii->pub.socitype) == SOCI_NAI)) {
1895 if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)
1900 ai_scan(&sii->pub, (void *)(uintptr)cc, devid);
1901 } else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
1904 ub_scan(&sii->pub, (void *)(uintptr)cc, devid);
1910 if (sii->numcores == 0) {
1916 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
1930 if ((sii->pub.ccrev == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||
1934 (CHIPREV(sii->pub.chiprev) <= 2))) {
1966 pcie_disable_TL_clk_gating(sii->pch);
1967 pcie_set_L1_entry_time(sii->pch, 0x40);
2010 if (CHIP_HOSTIF_PCIE(&(sii->pub))) {
2011 uint32 sflags = si_arm_sflags(&(sii->pub));
2030 nvram_init((void *)&(sii->pub));
2033 devinfo_nvram_init((void *)&(sii->pub));
2037 if (srom_var_init(&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) {
2043 si_nvram_process(sii, pvars);
2051 sii->pub.boardtype = getintvar(pvars, rstr_boardtype);
2076 if (sii->pub.ccrev >= 20) {
2096 si_pmu_init(sih, sii->osh);
2097 si_pmu_chip_init(sih, sii->osh);
2153 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
2161 si_pmu_pll_init(sih, sii->osh, xtalfreq);
2172 si_pmu_res_init(sih, sii->osh);
2174 si_pmu_swreg_init(sih, sii->osh);
2188 if (sii->pub.ccrev >= 16) {
2194 if (PCI_FORCEHT(sii)) {
2198 _si_clkctl_cc(sii, CLK_FAST);
2202 if (PCIE(sii)) {
2203 ASSERT(sii->pch != NULL);
2205 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
2241 si_muxenab((si_t *)sii, w);
2247 si_swdenable((si_t *)sii, w);
2270 si_muxenab((si_t *)sii, 3);
2272 return (sii);
2276 if (sii->pch)
2277 pcicore_deinit(sii->pch);
2278 sii->pch = NULL;
2288 si_info_t *sii;
2296 sii = SI_INFO(sih);
2298 if (sii == NULL)
2303 if (sii->regs[idx]) {
2304 REG_UNMAP(sii->regs[idx]);
2305 sii->regs[idx] = NULL;
2316 if (sii->pch)
2317 pcicore_deinit(sii->pch);
2318 sii->pch = NULL;
2322 if (sii != &ksii)
2324 MFREE(sii->osh, sii, sizeof(si_info_t));
2330 si_info_t *sii;
2332 sii = SI_INFO(sih);
2333 return sii->osh;
2339 si_info_t *sii;
2341 sii = SI_INFO(sih);
2342 if (sii->osh != NULL) {
2344 ASSERT(!sii->osh);
2346 sii->osh = osh;
2354 si_info_t *sii;
2356 sii = SI_INFO(sih);
2357 sii->intr_arg = intr_arg;
2358 sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn;
2359 sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn;
2360 sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn;
2364 sii->dev_coreid = sii->coreid[sii->curidx];
2370 si_info_t *sii;
2372 sii = SI_INFO(sih);
2373 sii->intrsoff_fn = NULL;
2374 sii->intrsrestore_fn = NULL;
2375 sii->intrsenabled_fn = NULL;
2381 si_info_t *sii = SI_INFO(sih);
2386 return R_REG(sii->osh, ((uint32 *)(uintptr)
2387 (sii->oob_router + OOB_STATUSA)));
2436 si_info_t *sii;
2438 sii = SI_INFO(sih);
2439 return sii->coreid[sii->curidx];
2445 si_info_t *sii;
2447 sii = SI_INFO(sih);
2448 return sii->curidx;
2455 si_info_t *sii;
2461 sii = SI_INFO(sih);
2464 idx = sii->curidx;
2466 ASSERT(GOODREGS(sii->curmap));
2471 if (sii->coreid[i] == coreid)
2518 si_info_t *sii;
2522 sii = SI_INFO(sih);
2526 for (i = 0; i < sii->numcores; i++)
2527 if (sii->coreid[i] == coreid) {
2540 si_info_t *sii;
2542 sii = SI_INFO(sih);
2544 bcopy((uchar*)sii->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));
2545 return (sii->numcores);
2552 si_info_t *sii;
2554 sii = SI_INFO(sih);
2555 ASSERT(GOODREGS(sii->curwrap));
2557 return (sii->curwrap);
2564 si_info_t *sii;
2566 sii = SI_INFO(sih);
2567 ASSERT(GOODREGS(sii->curmap));
2569 return (sii->curmap);
2618 si_info_t *sii = SI_INFO(sih);
2620 if (SI_FAST(sii)) {
2627 return (void *)CCREGS_FAST(sii);
2629 return (void *)PCIEREGS(sii);
2631 INTR_OFF(sii, *intr_val);
2632 *origidx = sii->curidx;
2643 si_info_t *sii;
2645 sii = SI_INFO(sih);
2646 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
2650 INTR_RESTORE(sii, intr_val);
3064 si_info_t *sii;
3065 sii = SI_INFO(sih);
3066 return (si_pmu_is_autoresetphyclk_disabled(sih, sii->osh));
3072 si_info_t *sii;
3086 sii = SI_INFO(sih);
3087 INTR_OFF(sii, intr_val);
3089 rate = si_pmu_si_clock(sih, sii->osh);
3093 idx = sii->curidx;
3097 n = R_REG(sii->osh, &cc->clockcontrol_n);
3100 m = R_REG(sii->osh, &cc->clockcontrol_m3);
3102 m = R_REG(sii->osh, &cc->clockcontrol_m2);
3104 m = R_REG(sii->osh, &cc->clockcontrol_sb);
3115 INTR_RESTORE(sii, intr_val);
3268 si_info_t *sii = SI_INFO(sih);
3293 else if ((device = (uint16)getintvar(sii->vars, rstr_devid)) != 0)
3296 else if ((device = (uint16)getintvar(sii->vars, rstr_wl0id)) != 0)
3469 si_info_t *sii = SI_INFO(sih);
3472 origidx = sii->curidx;
3474 INTR_OFF(sii, intr_val);
3485 INTR_RESTORE(sii, intr_val);
3492 si_slowclk_src(si_info_t *sii)
3496 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
3498 if (sii->pub.ccrev < 6) {
3499 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
3500 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &
3505 } else if (sii->pub.ccrev < 10) {
3506 cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);
3508 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
3515 si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
3520 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
3523 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
3525 slowclk = si_slowclk_src(sii);
3526 if (sii->pub.ccrev < 6) {
3531 } else if (sii->pub.ccrev < 10) {
3533 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
3544 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
3552 BCMINITFN(si_clkctl_setdelay)(si_info_t *sii, void *chipcregs)
3564 slowclk = si_slowclk_src(sii);
3569 slowmaxfreq = si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? FALSE : TRUE, cc);
3574 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
3575 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
3582 si_info_t *sii;
3590 sii = SI_INFO(sih);
3591 fast = SI_FAST(sii);
3593 origidx = sii->curidx;
3596 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
3602 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
3605 si_clkctl_setdelay(sii, (void *)(uintptr)cc);
3617 si_info_t *sii = SI_INFO(sih);
3626 INTR_OFF(sii, intr_val);
3627 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
3628 INTR_RESTORE(sii, intr_val);
3635 fast = SI_FAST(sii);
3638 origidx = sii->curidx;
3639 INTR_OFF(sii, intr_val);
3643 else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
3647 slowminfreq = si_slowclk_freq(sii, FALSE, cc);
3648 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
3654 INTR_RESTORE(sii, intr_val);
3663 si_info_t *sii;
3666 sii = SI_INFO(sih);
3677 if (PCIE(sii) || PCIE_GEN2(sii))
3680 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32));
3681 out = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32));
3682 outen = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32));
3703 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
3705 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
3713 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
3722 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32), out);
3723 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32),
3746 si_info_t *sii;
3748 sii = SI_INFO(sih);
3754 if (PCI_FORCEHT(sii))
3757 return _si_clkctl_cc(sii, mode);
3762 _si_clkctl_cc(si_info_t *sii, uint mode)
3768 bool fast = SI_FAST(sii);
3771 if (sii->pub.ccrev < 6)
3775 ASSERT(sii->pub.ccrev != 10);
3778 INTR_OFF(sii, intr_val);
3779 origidx = sii->curidx;
3781 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) &&
3782 si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
3783 (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
3786 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);
3787 } else if ((cc = (chipcregs_t *) CCREGS_FAST(sii)) == NULL)
3791 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
3796 if (sii->pub.ccrev < 10) {
3798 si_clkctl_xtal(&sii->pub, XTAL, ON);
3799 SET_REG(sii->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
3800 } else if (sii->pub.ccrev < 20) {
3801 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
3803 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
3807 if (PMUCTL_ENAB(&sii->pub)) {
3809 if (CHIPID(sii->pub.chip) == BCM4328_CHIP_ID)
3811 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0),
3813 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
3820 if (sii->pub.ccrev < 10) {
3821 scc = R_REG(sii->osh, &cc->slow_clk_ctl);
3825 W_REG(sii->osh, &cc->slow_clk_ctl, scc);
3829 si_clkctl_xtal(&sii->pub, XTAL, OFF);
3830 } else if (sii->pub.ccrev < 20) {
3832 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
3834 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
3838 if (PMUCTL_ENAB(&sii->pub)) {
3840 if (CHIPID(sii->pub.chip) == BCM4328_CHIP_ID)
3842 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) != 0),
3844 ASSERT(!(R_REG(sii->osh, &cc->clk_ctl_st) & htavail));
3857 si_setcoreidx(&sii->pub, origidx);
3858 INTR_RESTORE(sii, intr_val);
4087 si_info_t *sii;
4090 sii = SI_INFO(sih);
4096 reg_val = si_corereg(&sii->pub, SI_CC_IDX, offset, mask, val);
4153 si_info_t *sii;
4155 sii = SI_INFO(sih);
4161 W_REG(sii->osh, &cc->res_table_sel, int_val);
4162 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask);
4166 max_res_mask = R_REG(sii->osh, &cc->max_res_mask);
4168 W_REG(sii->osh, &cc->max_res_mask, max_res_mask);
4170 W_REG(sii->osh, &cc->min_res_mask, min_res_mask);
4177 si_info_t *sii;
4179 sii = SI_INFO(sih);
4184 min_res_mask = R_REG(sii->osh, &cc->min_res_mask);
4187 W_REG(sii->osh, &cc->res_table_sel, i);
4188 res_dep_mask = R_REG(sii->osh, &cc->res_dep_mask);
4262 si_info_t *sii;
4264 sii = SI_INFO(sih);
4266 if (!PCIE(sii)) {
4271 return pcicore_pciereg(sii->pch, offset, mask, val, type);
4277 si_info_t *sii;
4279 sii = SI_INFO(sih);
4281 if (!PCIE(sii)) {
4286 return pcicore_pcieserdesreg(sii->pch, mdioslave, offset, mask, val);
4292 si_ispcie(si_info_t *sii)
4296 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
4299 cap_ptr = pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, NULL);
4338 si_info_t *sii = SI_INFO(sih);
4342 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
4344 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
4352 si_info_t *sii = SI_INFO(sih);
4354 return (PCI(sii) && (sih->buscorerev <= 10));
4366 si_info_t *sii = SI_INFO(sih);
4368 if (!PCIE_GEN1(sii))
4371 pcie_war_ovr_aspm_update(sii->pch, aspm);
4377 si_info_t *sii = SI_INFO(sih);
4379 if (!PCIE_GEN1(sii))
4382 pcie_power_save_enable(sii->pch, enable);
4388 si_info_t *sii = SI_INFO(sih);
4390 if (!PCIE(sii))
4393 pcie_set_maxpayload_size(sii->pch, size);
4399 si_info_t *sii = SI_INFO(sih);
4401 if (!PCIE(sii))
4404 return pcie_get_maxpayload_size(sii->pch);
4410 si_info_t *sii = SI_INFO(sih);
4412 if (!PCIE(sii))
4415 pcie_set_request_size(sii->pch, size);
4421 si_info_t *sii = SI_INFO(sih);
4423 if (!PCIE_GEN1(sii))
4426 return pcie_get_request_size(sii->pch);
4433 si_info_t *sii = SI_INFO(sih);
4435 if (!PCIE_GEN1(sii))
4438 return pcie_get_ssid(sii->pch);
4444 si_info_t *sii = SI_INFO(sih);
4446 if (!PCIE(sii))
4449 return pcie_get_bar0(sii->pch);
4455 si_info_t *sii = SI_INFO(sih);
4457 if (!PCIE(sii))
4460 return pcie_configspace_cache(sii->pch);
4466 si_info_t *sii = SI_INFO(sih);
4468 if (!PCIE(sii))
4471 return pcie_configspace_restore(sii->pch);
4477 si_info_t *sii = SI_INFO(sih);
4479 if (!PCIE(sii) || size > PCI_CONFIG_SPACE_SIZE)
4482 return pcie_configspace_get(sii->pch, buf, size);
4489 si_info_t *sii = SI_INFO(sih);
4491 sii->pub.chippkg = val;
4497 si_info_t *sii = SI_INFO(sih);
4499 if (PCIE_GEN2(sii))
4500 pcie_hw_L1SS_war(sii->pch);
4506 si_info_t *sii;
4512 sii = SI_INFO(sih);
4514 if (PCI_FORCEHT(sii))
4515 _si_clkctl_cc(sii, CLK_FAST);
4517 if (PCIE(sii)) {
4518 pcicore_up(sii->pch, SI_PCIUP);
4521 sb_set_initiator_to((void *)sii, 0x3,
4522 si_findcoreidx((void *)sii, D11_CORE_ID, 0));
4539 si_info_t *sii = SI_INFO(sih);
4546 if (PCI_FORCEHT(sii))
4547 _si_clkctl_cc(sii, CLK_DYNAMIC);
4549 pcicore_down(sii->pch, SI_PCIDOWN);
4559 si_info_t *sii = SI_INFO(sih);
4564 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
4567 ASSERT(PCI(sii) || PCIE(sii));
4568 ASSERT(sii->pub.buscoreidx != BADIDX);
4570 if (PCI(sii)) {
4572 idx = sii->curidx;
4578 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx);
4585 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
4587 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32));
4593 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w);
4599 if (PCI(sii)) {
4600 OR_REG(sii->osh, &pciregs->sbtopci2, (SBTOPCI_PREF | SBTOPCI_BURST));
4601 if (sii->pub.buscorerev >= 11) {
4602 OR_REG(sii->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4603 w = R_REG(sii->osh, &pciregs->clkrun);
4604 W_REG(sii->osh, &pciregs->clkrun, (w | PCI_CLKRUN_DSBL));
4605 w = R_REG(sii->osh, &pciregs->clkrun);
4616 si_info_t *sii = SI_INFO(sih);
4618 if (!PCIE(sii))
4621 return pcie_clkreq(sii->pch, mask, val);
4627 si_info_t *sii = SI_INFO(sih);
4629 if (!PCIE(sii))
4632 return pcie_lcreg(sii->pch, mask, val);
4638 si_info_t *sii = SI_INFO(sih);
4640 if (!(PCIE(sii)))
4643 return pcie_ltrenable(sii->pch, mask, val);
4649 si_info_t *sii;
4651 sii = SI_INFO(sih);
4653 if (!(PCIE(sii)))
4656 return pcie_obffenable(sii->pch, mask, val);
4662 si_info_t *sii = SI_INFO(sih);
4664 if (!(PCIE(sii)))
4667 return pcie_ltr_reg(sii->pch, reg, mask, val);
4673 si_info_t *sii = SI_INFO(sih);
4675 if (!(PCIE(sii)))
4678 return pcieltrspacing_reg(sii->pch, mask, val);
4684 si_info_t *sii = SI_INFO(sih);
4686 if (!(PCIE(sii)))
4689 return pcieltrhysteresiscnt_reg(sii->pch, mask, val);
4695 si_info_t *sii = SI_INFO(sih);
4697 if (!PCIE(sii))
4700 pcie_set_error_injection(sii->pch, mode);
4706 si_info_t *sii;
4708 sii = SI_INFO(sih);
4710 if (PCIE_GEN2(sii))
4711 pcie_set_L1substate(sii->pch, substate);
4717 si_info_t *sii;
4719 sii = SI_INFO(sih);
4721 if (PCIE_GEN2(sii))
4722 return pcie_get_L1substate(sii->pch);
4759 si_info_t *sii = SI_INFO(sih);
4761 ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS);
4763 if ((CHIPID(sii->pub.chip) == BCM4321_CHIP_ID) && (CHIPREV(sii->pub.chiprev) < 2)) {
4764 w = (CHIPREV(sii->pub.chiprev) == 0) ?
4766 si_corereg(&sii->pub, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), ~0, w);
4770 origidx = si_coreidx(&sii->pub);
4772 if (sii->pub.buscoretype == PCIE2_CORE_ID) {
4773 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE2_CORE_ID, 0);
4776 } else if (sii->pub.buscoretype == PCIE_CORE_ID) {
4777 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE_CORE_ID, 0);
4780 } else if (sii->pub.buscoretype == PCI_CORE_ID) {
4781 pciregs = (sbpciregs_t *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
4785 pciidx = si_coreidx(&sii->pub);
4789 val16 = R_REG(sii->osh, reg16);
4793 W_REG(sii->osh, reg16, val16);
4797 si_setcoreidx(&sii->pub, origidx);
4799 pcicore_hwup(sii->pch);
4806 si_info_t *sii = SI_INFO(sih);
4808 if (!PCIE_GEN1(sii) && !PCIE_GEN2(sii))
4811 return pcicore_dump_pcieinfo(sii->pch, b);
5055 si_info_t *sii;
5061 sii = SI_INFO(sih);
5065 if ((gi = MALLOC(sii->osh, sizeof(gpioh_item_t))) == NULL)
5074 gi->next = sii->gpioh_head;
5075 sii->gpioh_head = gi;
5083 si_info_t *sii;
5089 sii = SI_INFO(sih);
5090 ASSERT(sii->gpioh_head != NULL);
5091 if ((void*)sii->gpioh_head == gpioh) {
5092 sii->gpioh_head = sii->gpioh_head->next;
5093 MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
5096 p = sii->gpioh_head;
5101 MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
5115 si_info_t *sii = SI_INFO(sih);
5122 for (h = sii->gpioh_head; h != NULL; h = h->next) {
5151 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 idx, uint8 mem_type)
5158 W_REG(sii->osh, ®s->bankidx, bankidx);
5159 bankinfo = R_REG(sii->osh, ®s->bankinfo);
5167 si_info_t *sii = SI_INFO(sih);
5175 INTR_OFF(sii, intr_val);
5196 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
5200 W_REG(sii->osh, ®s->bankidx, bankidx);
5201 bankinfo = R_REG(sii->osh, ®s->bankinfo);
5214 W_REG(sii->osh, ®s->bankinfo, bankinfo);
5234 INTR_RESTORE(sii, intr_val);
5240 si_info_t *sii = SI_INFO(sih);
5252 INTR_OFF(sii, intr_val);
5265 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
5269 W_REG(sii->osh, ®s->bankidx, bankidx);
5270 bankinfo = R_REG(sii->osh, ®s->bankinfo);
5284 INTR_RESTORE(sii, intr_val);
5300 si_info_t *sii = SI_INFO(sih);
5309 INTR_OFF(sii, intr_val);
5326 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
5329 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
5338 INTR_RESTORE(sii, intr_val);
5346 si_info_t *sii = SI_INFO(sih);
5359 INTR_OFF(sii, intr_val);
5372 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
5384 W_REG(sii->osh, ®s->bankidx, bankidx);
5385 bankinfo = R_REG(sii->osh, ®s->bankinfo);
5387 banksz = socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
5402 INTR_RESTORE(sii, intr_val);
5411 si_info_t *sii = SI_INFO(sih);
5422 INTR_OFF(sii, intr_val);
5433 coreinfo = R_REG(sii->osh, ®s->coreinfo);
5454 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
5463 INTR_RESTORE(sii, intr_val);
5474 si_info_t *sii;
5490 sii = SI_INFO(sih);
5493 INTR_OFF(sii, intr_val);
5507 corecap = R_REG(sii->osh, arm_cap_reg);
5516 W_REG(sii->osh, arm_bidx, idx);
5518 bxinfo = R_REG(sii->osh, arm_binfo);
5528 INTR_RESTORE(sii, intr_val);
5554 si_info_t *sii;
5568 sii = SI_INFO(sih);
5571 INTR_OFF(sii, intr_val);
5582 coreinfo = R_REG(sii->osh, ®s->coreinfo);
5589 W_REG(sii->osh, ®s->bankidx, i);
5590 if (R_REG(sii->osh, ®s->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK)
5591 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
5601 INTR_RESTORE(sii, intr_val);
5673 si_info_t *sii;
5682 sii = SI_INFO(sih);
5683 fast = SI_FAST(sii);
5685 origidx = sii->curidx;
5688 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
5694 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskhi, 0x0);
5695 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskmi, 0x0);
5696 W_REG(sii->osh, &cc->eci.lt35.eci_intmasklo, 0x0);
5699 W_REG(sii->osh, &cc->eci.ge35.eci_intmaskhi, 0x0);
5700 W_REG(sii->osh, &cc->eci.ge35.eci_intmasklo, 0x0);
5705 W_REG(sii->osh, &cc->eci.lt35.eci_control, ECI_MACCTRL_BITS);
5708 W_REG(sii->osh, &cc->eci.ge35.eci_controllo, ECI_MACCTRLLO_BITS);
5709 W_REG(sii->osh, &cc->eci.ge35.eci_controlhi, ECI_MACCTRLHI_BITS);
5716 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskhi, 0x0);
5717 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskmi, 0x0);
5718 W_REG(sii->osh, &cc->eci.lt35.eci_eventmasklo, 0x0);
5721 W_REG(sii->osh, &cc->eci.ge35.eci_eventmaskhi, 0x0);
5722 W_REG(sii->osh, &cc->eci.ge35.eci_eventmasklo, 0x0);
5832 si_info_t *sii;
5840 sii = SI_INFO(sih);
5841 fast = SI_FAST(sii);
5844 origidx = sii->curidx;
5847 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
5853 seci_conf = R_REG(sii->osh, &cc->SECI_config);
5855 W_REG(sii->osh, &cc->SECI_config, seci_conf);
5856 SPINWAIT((R_REG(sii->osh, &cc->SECI_config) & SECI_UPD_SECI), 1000);
5859 W_REG(sii->osh, &cc->seci_uart_data, SECI_SIGNOFF_0);
5860 W_REG(sii->osh, &cc->seci_uart_data, SECI_SIGNOFF_1);
5861 SPINWAIT((R_REG(sii->osh, &cc->seci_uart_lsr) & (1 << 2)), 1000);
5863 seci_conf = R_REG(sii->osh, &cc->SECI_config);
5865 W_REG(sii->osh, &cc->SECI_config, seci_conf);
5867 W_REG(sii->osh, &cc->SECI_config, seci_conf);
5882 si_info_t *sii;
5891 sii = SI_INFO(sih);
5892 fast = SI_FAST(sii);
5893 INTR_OFF(sii, intr_val);
5895 origidx = sii->curidx;
5898 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
5907 regval = R_REG(sii->osh, &cc->chipcontrol);
5920 W_REG(sii->osh, &cc->chipcontrol, regval);
5924 regval = R_REG(sii->osh, &cc->SECI_config);
5926 W_REG(sii->osh, &cc->SECI_config, regval);
5927 SPINWAIT((R_REG(sii->osh, &cc->SECI_config) & SECI_UPD_SECI), 1000);
5929 W_REG(sii->osh, &cc->seci_uart_data, SECI_SLIP_ESC_CHAR);
5930 W_REG(sii->osh, &cc->seci_uart_data, SECI_REFRESH_REQ);
5939 INTR_RESTORE(sii, intr_val);
5948 si_info_t *sii;
5964 sii = SI_INFO(sih);
5965 fast = SI_FAST(sii);
5967 origidx = sii->curidx;
5970 } else if ((ptr = CCREGS_FAST(sii)) == NULL)
5979 regval = R_REG(sii->osh, &cc->chipcontrol);
5981 W_REG(sii->osh, &cc->chipcontrol, regval);
5986 regval = R_REG(sii->osh, &cc->chipcontrol);
5998 W_REG(sii->osh, &cc->chipcontrol, regval);
6003 regval = R_REG(sii->osh, &cc->jtagctrl);
6005 W_REG(sii->osh, &cc->jtagctrl, regval);
6013 seci_conf = R_REG(sii->osh, &cc->SECI_config);
6015 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6017 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6026 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6030 seci_conf = R_REG(sii->osh, &cc->SECI_config);
6032 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6081 seci_conf = R_REG(sii->osh, &cc->SECI_config);
6084 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6087 seci_conf = R_REG(sii->osh, &cc->SECI_config);
6089 W_REG(sii->osh, &cc->SECI_config, seci_conf);
6102 si_info_t *sii = SI_INFO(sih);
6119 hndgci_init(sih, sii->osh, HND_GCI_PLAIN_UART_MODE,
6131 si_info_t *sii;
6142 sii = SI_INFO(sih);
6145 INTR_OFF(sii, intr_val);
6152 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04);
6157 INTR_RESTORE(sii, intr_val);
6163 si_info_t *sii = SI_INFO(sih);
6169 INTR_OFF(sii, intr_val);
6175 val = R_REG(sii->osh, &cc->chipcontrol);
6181 W_REG(sii->osh, &cc->chipcontrol, val);
6184 W_REG(sii->osh, &cc->chipcontrol, val);
6190 INTR_RESTORE(sii, intr_val);
6196 si_info_t *sii = SI_INFO(sih);
6201 W_REG(sii->osh, &cc->chipcontrol, val);
6208 si_info_t *sii = SI_INFO(sih);
6214 val = R_REG(sii->osh, &cc->chipcontrol);
6222 si_info_t *sii = SI_INFO(sih);
6228 val = R_REG(sii->osh, &cc->chipcontrol);
6234 W_REG(sii->osh, &cc->chipcontrol, val);
6238 W_REG(sii->osh, &cc->chipcontrol, val |
6241 W_REG(sii->osh, &cc->chipcontrol, val | (CCTRL4331_EXTPA_EN));
6246 W_REG(sii->osh, &cc->chipcontrol, val);
6256 si_info_t *sii = SI_INFO(sih);
6262 val = R_REG(sii->osh, &cc->chipcontrol);
6271 W_REG(sii->osh, &cc->chipcontrol, val);
6281 si_info_t *sii;
6294 sii = SI_INFO(sih);
6299 val = R_REG(sii->osh, &cc->chipcontrol);
6303 W_REG(sii->osh, &cc->chipcontrol, val);
6306 W_REG(sii->osh, &cc->chipcontrol, val);
6318 si_info_t *sii = SI_INFO(sih);
6320 INTR_OFF(sii, intr_val);
6321 err = si_pll_minresmask_reset(sih, sii->osh);
6322 INTR_RESTORE(sii, intr_val);
6330 si_info_t *sii = SI_INFO(sih);
6337 W_REG(sii->osh, &cc->gpiocontrol,
6338 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
6346 si_info_t *sii = SI_INFO(sih);
6348 si_pmu_minresmask_htavail_set(sih, sii->osh, set_clear);
6355 si_info_t *sii = SI_INFO(sih);
6357 OR_REG(sii->osh, PMUREG(sih, min_res_mask), PMURES_BIT(RES4313_SYNTH_PWRSW_RSRC));
6364 si_info_t *sii = SI_INFO(sih);
6369 W_REG(sii->osh, &cc->gpiocontrol,
6370 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_5_6_EN_MASK);
6372 W_REG(sii->osh, &cc->gpioouten,
6373 R_REG(sii->osh, &cc->gpioouten) | GPIO_CTRL_5_6_EN_MASK);
6380 si_info_t *sii = SI_INFO(sih);
6387 W_REG(sii->osh, &cc->chipcontrol,
6388 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK);
6395 si_info_t *sii = SI_INFO(sih);
6401 W_REG(sii->osh, &cc->gpioouten, GPIO_CTRL_7_6_EN_MASK);
6402 W_REG(sii->osh, &cc->gpioout, GPIO_OUT_7_EN_MASK);
6428 si_info_t *sii;
6436 sii = SI_INFO(sih);
6437 origidx = sii->curidx;
6440 sromctrl = R_REG(sii->osh, &cc->sromcontrol);
6897 si_info_t *sii = SI_INFO(sih);
6901 INTR_OFF(sii, intr_val);
6908 INTR_RESTORE(sii, intr_val);
6920 si_info_t *sii = SI_INFO(sih);
6935 si_pmu_res_minmax_update(sih, sii->osh);
6940 si_pmu_res_minmax_update(sih, sii->osh);
6952 si_pmu_res_minmax_update(sih, sii->osh);
7042 si_info_t *sii = SI_INFO(sih);
7044 if (!PCIE(sii))
7050 return pcie_set_ctrlreg(sii->pch, mask, val);
7057 si_info_t *sii;
7059 sii = SI_INFO(sih);
7061 if (!PCIE(sii))
7064 return pcie_survive_perst(sii->pch, mask, val);
7070 si_info_t *sii = SI_INFO(sih);
7074 W_REG(sii->osh, PMUREG(sih, pmuwatchdog), 2);
7094 si_info_t *sii = SI_INFO(sih);
7098 bar0win = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
7102 bar0win_after = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
7106 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), bar0win);
7119 si_info_t *sii = SI_INFO(sih);
7121 if (PCIE_GEN2(sii))
7122 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0));
7128 si_info_t *sii = SI_INFO(sih);
7130 if (PCIE_GEN2(sii))
7131 pcie_hw_LTR_war(sii->pch);
7137 si_info_t *sii = SI_INFO(sih);
7139 if (PCIE_GEN2(sii))
7140 pciedev_reg_pm_clk_period(sii->pch);
7146 si_info_t *sii = SI_INFO(sih);
7148 if (PCIE_GEN2(sii))
7149 pciedev_crwlpciegen2(sii->pch);
7155 si_info_t *sii = SI_INFO(sih);
7157 if (PCIE_GEN2(sii))
7158 pciedev_prep_D3(sii->pch, enter_D3);