Lines Matching refs:sih
85 static void si_sromvars_fixup_4331(si_t *sih, char *pvars);
89 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);
90 static char *si_pcie_devpathvar(si_t *sih, char *var, int len, const char *name);
94 void si_gci_chipctrl_overrides(osl_t *osh, si_t *sih, char *pvars);
98 static uint8 si_gci_gpio_wakemask(si_t *sih, uint8 gpio, uint8 mask, uint8 value);
99 static uint8 si_gci_gpio_intmask(si_t *sih, uint8 gpio, uint8 mask, uint8 value);
100 uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
104 static uint si_get_uart_clock(si_t *sih, osl_t *osh, chipcregs_t *cc);
211 si_ldo_war(si_t *sih, uint devid)
213 si_info_t *sii = SI_INFO(sih);
237 W_REG(sii->osh, PMUREG(sih, regcontrol_addr), 0);
238 /* AND_REG(sii->osh, PMUREG(sih, regcontrol_data), ~0x80); */
239 W_REG(sii->osh, PMUREG(sih, regcontrol_data), 0x3001);
244 W_REG(sii->osh, PMUREG(sih, min_res_mask), 0x0d);
456 struct si_pub *sih = &sii->pub;
459 if (BUSTYPE(sih->bustype) != PCI_BUS)
462 if ((CHIPID(sih->chip) != BCM4331_CHIP_ID) && (CHIPID(sih->chip) != BCM43431_CHIP_ID))
466 if (sih->chippkg != 9)
583 BCMATTACHFN(si_sromvars_fixup_4331)(si_t *sih, char *pvars)
590 uint boardtype = sih->boardtype;
591 uint boardrev = sih->boardrev;
651 BCMATTACHFN(si_swdenable)(si_t *sih, uint32 swdflag)
653 switch (CHIPID(sih->chip)) {
659 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT),
664 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT,
669 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, jtagctrl),
684 BCMATTACHFN(si_muxenab)(si_t *sih, uint32 w)
688 pmu_chipcontrol = si_pmu_chipcontrol(sih, 1, 0, 0);
689 chipcontrol = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
692 switch (CHIPID(sih->chip)) {
784 si_gci_set_functionsel(sih, CC4335_PIN_GPIO_09, 3);
785 si_gci_set_functionsel(sih, CC4335_PIN_GPIO_10, 3);
807 si_gci_set_functionsel(sih, uart_rx, CC4335_FNSEL_UART);
808 si_gci_set_functionsel(sih, uart_tx, CC4335_FNSEL_UART);
811 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06,
833 si_gci_set_functionsel(sih, hostwake, CC4335_FNSEL_MISC1);
858 if ((CHIPREV(sih->chiprev) >= 3) ||
859 (CHIPID(sih->chip) == BCM4354_CHIP_ID) ||
860 (CHIPID(sih->chip) == BCM4356_CHIP_ID) ||
861 (CHIPID(sih->chip) == BCM43569_CHIP_ID) ||
862 (CHIPID(sih->chip) == BCM43570_CHIP_ID)) {
863 si_gci_set_functionsel(sih, uart_rx, CC4350C_FNSEL_UART);
864 si_gci_set_functionsel(sih, uart_tx, CC4350C_FNSEL_UART);
867 si_gci_set_functionsel(sih, uart_rx, CC4350_FNSEL_UART);
868 si_gci_set_functionsel(sih, uart_tx, CC4350_FNSEL_UART);
890 si_gci_set_functionsel(sih, hostwake, CC4350_FNSEL_MISC1);
901 si_pmu_chipcontrol(sih, 1, ~0, pmu_chipcontrol);
902 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
908 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val)
911 return si_corereg(sih, SI_CC_IDX, offset, mask, val);
915 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val)
918 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, regidx);
919 return si_corereg(sih, SI_CC_IDX, offset, mask, val);
923 si_gci_input(si_t *sih, uint reg)
926 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_input[reg]), 0, 0);
930 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val)
933 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_output[reg]), mask, val);
937 si_gci_int_enable(si_t *sih, bool enable)
943 return (si_corereg(sih, SI_CC_IDX, offs, CI_ECI, (enable ? CI_ECI : 0)));
947 si_gci_reset(si_t *sih)
952 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl),
955 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl), ALLONES_32, 0x00);
959 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_event[i]), ALLONES_32, 0x00);
963 si_gci_gpio_chipcontrol(si_t *sih, uint8 gci_gpio, uint8 opt)
971 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
972 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpioctl),
978 si_gci_gpio_reg(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value, uint32 reg_offset)
986 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
990 si_corereg(sih, SI_CC_IDX, reg_offset, GCIMASK_4B(pos), GCIPOSVAL_4B(value, pos));
992 val_32 = si_corereg(sih, SI_CC_IDX, reg_offset, 0, 0);
1000 si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value)
1007 si_gci_set_functionsel(sih, gpio, CC4345_FNSEL_SAMEASPIN);
1008 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
1010 si_gpiocontrol(sih, mask, 0, GPIO_HI_PRIORITY);
1011 si_gpioouten(sih, mask, mask, GPIO_HI_PRIORITY);
1012 si_gpioout(sih, mask, value, GPIO_HI_PRIORITY);
1018 BCMATTACHFN(si_gci_host_wake_gpio_init)(si_t *sih)
1029 switch (CHIPID(sih->chip)) {
1033 si_gci_enable_gpio(sih, host_wake_gpio,
1037 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip)));
1044 si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state)
1046 switch (CHIPID(sih->chip)) {
1049 si_gci_enable_gpio(sih, gpio, 1 << gpio,
1053 SI_ERROR(("host wake not supported for 0x%04x yet\n", CHIPID(sih->chip)));
1059 si_gci_gpio_wakemask(si_t *sih, uint8 gpio, uint8 mask, uint8 value)
1061 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_wakemask),
1063 return (si_gci_gpio_reg(sih, gpio, mask, value, OFFSETOF(chipcregs_t, gci_gpiowakemask)));
1067 si_gci_gpio_intmask(si_t *sih, uint8 gpio, uint8 mask, uint8 value)
1069 return (si_gci_gpio_reg(sih, gpio, mask, value, OFFSETOF(chipcregs_t, gci_gpiointmask)));
1073 si_gci_gpio_status(si_t *sih, uint8 gpio, uint8 mask, uint8 value)
1075 return (si_gci_gpio_reg(sih, gpio, mask, value, OFFSETOF(chipcregs_t, gci_gpiostatus)));
1079 si_gci_enable_gpioint(si_t *sih, bool enable)
1082 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intmask),
1085 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intmask),
1091 BCMATTACHFN(si_enable_device_wake)(si_t *sih, uint8 *wake_mask, uint8 *cur_status)
1106 switch (CHIPID(sih->chip)) {
1110 si_gci_set_functionsel(sih, 1, CC4345_FNSEL_GCI0);
1111 si_gci_gpio_chipcontrol(sih, gci_gpio,
1118 si_gci_gpio_intmask(sih, gci_gpio, *wake_mask, *wake_mask);
1119 si_gci_gpio_wakemask(sih, gci_gpio, *wake_mask, *wake_mask);
1122 *cur_status = si_gci_gpio_status(sih, gci_gpio,
1125 si_gci_enable_gpioint(sih, TRUE);
1128 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, (1 << 31), (1 << 31));
1132 CHIPID(sih->chip), device_wake_opt));
1147 si_gci_gpio_chipcontrol(sih, gci_gpio, gpioctl_opt);
1152 reg = si_gci_gpio_intmask(sih, gci_gpio,
1157 reg = si_gci_gpio_wakemask(sih, gci_gpio,
1162 *cur_status = si_gci_gpio_status(sih, gci_gpio,
1166 si_gci_indirect(sih, 0,
1172 si_gci_indirect(sih, 0,
1179 si_pmu_chipcontrol(sih, 2, ~0, pmu_chipcontrol2);
1180 reg = si_pmu_chipcontrol(sih, 2, 0, 0);
1184 si_gci_int_enable(sih, TRUE);
1189 SI_ERROR(("device wake not supported for 0x%04x yet\n", CHIPID(sih->chip)));
1195 BCMATTACHFN(si_gci_gpioint_handler_unregister)(si_t *sih, void *gci_i)
1200 sii = SI_INFO(sih);
1204 sii = SI_INFO(sih);
1206 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) {
1232 BCMATTACHFN(si_gci_gpioint_handler_register)(si_t *sih, uint8 gci_gpio, uint8 gpio_status,
1238 sii = SI_INFO(sih);
1242 sii = SI_INFO(sih);
1244 if (!(sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)) {
1279 si_gci_gpioint_handler_process(si_t *sih)
1285 sii = SI_INFO(sih);
1290 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, 0);
1291 gpio_status[0] = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), 0, 0);
1292 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), ~0, ~0);
1294 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, 1);
1295 gpio_status[1] = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), 0, 0);
1296 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), ~0, ~0);
1312 si_gci_gpio_status(sih, gci_i->gci_gpio,
1319 si_gci_handler_process(si_t *sih)
1324 gci_intstatus = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intstat), 0, 0);
1328 si_gci_gpioint_handler_process(sih);
1332 hndgci_handler_process(gci_intstatus, sih);
1349 si_gci_seci_init(si_t *sih)
1351 if (CHIPID(sih->chip) == BCM4335_CHIP_ID ||
1352 CHIPID(sih->chip) == BCM4345_CHIP_ID) {
1354 si_gci_reset(sih);
1357 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl), ALLONES_32,
1360 si_gci_set_functionsel(sih, CC4335_PIN_GPIO_04, CC4335_FNSEL_GCI0);
1361 si_gci_set_functionsel(sih, CC4335_PIN_GPIO_05, CC4335_FNSEL_GCI0);
1363 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_miscctl), 0x0000000C, 0x0000);
1364 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secibauddiv), ALLONES_32, 0xF4);
1365 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secifcr), ALLONES_32, 0x00);
1366 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secimcr), ALLONES_32, 0x89);
1367 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secilcr), ALLONES_32, 0x28);
1368 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_uartescval), ALLONES_32, 0xDB);
1369 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_baudadj), ALLONES_32, 0x22);
1374 si_gci_indirect(sih, 0,
1376 si_gci_indirect(sih, 1,
1378 si_gci_indirect(sih, 2,
1383 si_gci_indirect(sih, 0,
1385 si_gci_indirect(sih, 1,
1391 si_gci_indirect(sih, 0,
1393 si_gci_indirect(sih, 4,
1398 si_gci_direct(sih,
1404 si_gci_direct(sih,
1410 si_ercx_init(si_t *sih, uint32 ltecx_mux)
1416 if (CHIPID(sih->chip) == BCM4334_CHIP_ID) {
1418 si_pmu_chipcontrol(sih, PMU1_PLL0_CHIPCTL1, 0x0000000F, 0x0000000A);
1420 else if (CHIPID(sih->chip) == BCM4335_CHIP_ID ||
1421 CHIPID(sih->chip) == BCM4345_CHIP_ID ||
1422 CHIPID(sih->chip) == BCM4350_CHIP_ID ||
1423 CHIPID(sih->chip) == BCM4354_CHIP_ID ||
1424 CHIPID(sih->chip) == BCM4356_CHIP_ID) {
1426 si_gci_reset(sih);
1429 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl),
1453 si_gci_clear_functionsel(sih, CC4350_FNSEL_GCI);
1457 si_gci_set_functionsel(sih, fsync_gpio, CC4350_FNSEL_GCI);
1458 si_gci_set_functionsel(sih, lterx_gpio, CC4350_FNSEL_GCI);
1459 si_gci_set_functionsel(sih, ltetx_gpio, CC4350_FNSEL_GCI);
1460 si_gci_set_functionsel(sih, wlprio_gpio, CC4350_FNSEL_GCI);
1465 si_gci_indirect(sih, temp_gpiomask,
1468 si_gci_indirect(sih, temp_gpio/4, OFFSETOF(chipcregs_t, gci_gpioctl),
1474 si_gci_indirect(sih, temp_gpiomask,
1477 si_gci_indirect(sih, temp_gpio/4, OFFSETOF(chipcregs_t, gci_gpioctl),
1483 si_gci_indirect(sih, temp_gpiomask,
1486 si_gci_indirect(sih, temp_gpio/4, OFFSETOF(chipcregs_t, gci_gpioctl),
1493 si_gci_indirect(sih, temp_gpiomask,
1496 si_gci_indirect(sih, temp_gpio/4, OFFSETOF(chipcregs_t, gci_gpioctl),
1502 si_wci2_init(si_t *sih, uint baudrate, uint32 ltecx_mux)
1510 si_gci_reset(sih);
1515 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl), ALLONES_32,
1521 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_corectrl), ALLONES_32,
1530 si_gci_clear_functionsel(sih, fnselin);
1532 si_gci_clear_functionsel(sih, fnselout);
1533 si_gci_set_functionsel(sih, uartin, fnselin);
1534 si_gci_set_functionsel(sih, uartout, fnselout);
1537 si_gci_indirect(sih, 0x00010, OFFSETOF(chipcregs_t, gci_inbandeventintmask),
1540 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_miscctl), 0x000C, 0x0000);
1541 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secifcr), ALLONES_32, 0x00);
1542 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secilcr), ALLONES_32, 0x28);
1543 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_uartescval), ALLONES_32, 0xDB);
1548 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secibauddiv),
1550 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secimcr),
1552 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_baudadj),
1558 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secibauddiv),
1560 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secimcr),
1562 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_baudadj),
1568 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secibauddiv),
1570 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secimcr),
1572 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_baudadj),
1579 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secibauddiv),
1581 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_secimcr),
1583 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_baudadj),
1590 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_rxfifo_common_ctrl),
1596 si_gci_indirect(sih, 0,
1598 si_gci_indirect(sih, 1,
1603 si_gci_indirect(sih, 0x70010,
1605 si_gci_indirect(sih, 0x60010,
1607 si_gci_indirect(sih, 0x50010,
1609 si_gci_indirect(sih, 0x40010,
1611 si_gci_indirect(sih, 0x30010,
1614 si_gci_indirect(sih, 0x50000,
1616 si_gci_indirect(sih, 0x40000,
1619 si_gci_direct(sih,
1661 si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode)
1664 hndgci_init(sih, osh, HND_GCI_PLAIN_UART_MODE,
1674 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
1678 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, reg);
1679 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_chipctrl), mask, val);
1688 si_gci_chipstatus(si_t *sih, uint reg)
1692 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, reg);
1694 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_chipsts), 0, 0);
1735 si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel)
1742 si_gci_chipcontrol(sih, reg, GCIMASK_4B(pos), GCIPOSVAL_4B(fnsel, pos));
1747 si_gci_get_functionsel(si_t *sih, uint32 pin)
1754 temp = si_gci_chipstatus(sih, reg);
1760 si_gci_clear_functionsel(si_t *sih, uint8 fnsel)
1765 if (si_gci_get_functionsel(sih, i) == fnsel)
1766 si_gci_set_functionsel(sih, i, CC4335_FNSEL_IND);
1771 BCMATTACHFN(si_gci_chipctrl_overrides)(osl_t *osh, si_t *sih, char *pvars)
1781 cap1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_corecaps1), 0, 0);
1794 si_gci_chipcontrol(sih, i, ~0, gciccval);
1808 struct si_pub *sih = &sii->pub;
1823 sih->buscoreidx = BADIDX;
1830 si_enum_base_init(sih, bustype);
1854 sih->bustype = bustype;
1877 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
1879 sih->chip = w & CID_ID_MASK;
1880 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
1881 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
1883 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (sih->chiprev == 0) &&
1884 (sih->chippkg != BCM4329_289PIN_PKG_ID)) {
1885 sih->chippkg = BCM4329_182PIN_PKG_ID;
1887 sih->issim = IS_SIM(sih->chippkg);
1902 SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip));
1922 if (CHIPID(sih->chip) == BCM4322_CHIP_ID && (((sih->chipst & CST4322_SPROM_OTP_SEL_MASK)
1930 if ((sii->pub.ccrev == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||
1931 CHIPID(sih->chip) == BCM43235_CHIP_ID ||
1932 CHIPID(sih->chip) == BCM43234_CHIP_ID ||
1933 CHIPID(sih->chip) == BCM43238_CHIP_ID) &&
1948 if ((CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
1949 (CHIPID(sih->chip) == BCM43431_CHIP_ID)) {
1951 if (sih->chippkg == 9) {
1952 uint32 val = si_chipcontrl_read(sih);
1957 si_chipcontrl_epa4331(sih, FALSE);
1958 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 100);
1962 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
1963 (CHIPID(sih->chip) == BCM43460_CHIP_ID) ||
1964 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) &&
1965 (CHIPREV(sih->chiprev) <= 2)) {
1978 if ((CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
1979 (CHIPID(sih->chip) == BCM43142_CHIP_ID)) {
1981 } else if ((CHIPID(sih->chip) == BCM43131_CHIP_ID) ||
1982 (CHIPID(sih->chip) == BCM43217_CHIP_ID) ||
1983 (CHIPID(sih->chip) == BCM43227_CHIP_ID) ||
1984 (CHIPID(sih->chip) == BCM43228_CHIP_ID)) {
1990 savecore = si_coreidx(sih);
1991 si_setcore(sih, CC_CORE_ID, 0);
1998 si_setcoreidx(sih, savecore);
2019 hnd_cpu_wait(sih);
2025 si_sprom_init(sih);
2047 if ((CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
2048 (CHIPID(sih->chip) == BCM43431_CHIP_ID)) {
2049 si_sromvars_fixup_4331(sih, pvars);
2068 hnd_tcam_bootloader_load(si_setcore(sih, ARMCR4_CORE_ID, 0), pvars);
2070 hnd_tcam_bootloader_load(si_setcore(sih, SOCRAM_CORE_ID, 0), pvars);
2072 si_setcoreidx(sih, origidx);
2078 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
2082 if ((CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
2083 (CHIPID(sih->chip) == BCM43142_CHIP_ID)) {
2090 si_setcoreidx(sih, origidx);
2094 if (PMUCTL_ENAB(sih)) {
2096 si_pmu_init(sih, sii->osh);
2097 si_pmu_chip_init(sih, sii->osh);
2099 switch (CHIPID(sih->chip)) {
2121 mode = CST4350_IFC_MODE(sih->chipst);
2131 if (((CHIPREV(sih->chiprev) >= 3) ||
2132 (CHIPID(sih->chip) ==
2134 (CHIPID(sih->chip) ==
2136 (CHIPID(sih->chip) ==
2138 (CHIPID(sih->chip) ==
2140 CST4350_PKG_USB_40M(sih->chipst) &&
2141 CST4350_PKG_USB(sih->chipst)) {
2153 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
2156 if ((xtalfreq == 0) && (CHIPID(sih->chip) == BCM4345_CHIP_ID)) {
2161 si_pmu_pll_init(sih, sii->osh, xtalfreq);
2169 sr_save_restore_init(sih);
2172 si_pmu_res_init(sih, sii->osh);
2174 si_pmu_swreg_init(sih, sii->osh);
2179 if ((CHIPID(sih->chip) != BCM4335_CHIP_ID) &&
2182 si_lowpwr_opt(sih);
2191 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
2196 sih->pci_pr32414 = TRUE;
2197 si_clkctl_init(sih);
2207 if (((CHIPID(sih->chip) == BCM4311_CHIP_ID) && (CHIPREV(sih->chiprev) == 2)) ||
2208 (CHIPID(sih->chip) == BCM4312_CHIP_ID)) {
2210 sb_set_initiator_to(sih, 0x3, si_findcoreidx(sih, D11_CORE_ID, 0));
2214 if ((CHIPID(sih->chip) == BCM43224_CHIP_ID) ||
2215 (CHIPID(sih->chip) == BCM43421_CHIP_ID)) {
2217 if (CHIPREV(sih->chiprev) == 0) {
2219 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
2221 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
2224 if (CHIPREV(sih->chiprev) >= 1) {
2226 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
2232 if (BCM4350_CHIP(sih->chip) && CHIP_HOSTIF_USB(sih)) {
2233 si_gci_set_functionsel(sih, CC4350_PIN_GPIO_13, CC4350_FNSEL_SAMEASPIN);
2234 si_gci_set_functionsel(sih, CC4350_PIN_GPIO_14, CC4350_FNSEL_SAMEASPIN);
2235 si_gci_set_functionsel(sih, CC4350_PIN_GPIO_15, CC4350_FNSEL_SAMEASPIN);
2250 if (CHIPID(sih->chip) == BCM4313_CHIP_ID) {
2253 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE, CCTRL_4313_12MA_LED_DRIVE);
2257 ASSERT(!si_taclear(sih, FALSE));
2259 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
2260 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
2262 BCM4350_CHIP(sih->chip) ||
2265 si_gci_chipctrl_overrides(osh, sih, pvars);
2275 if (BUSTYPE(sih->bustype) == PCI_BUS) {
2286 BCMATTACHFN(si_detach)(si_t *sih)
2293 bcopy(&sih, &si_local, sizeof(si_t*));
2296 sii = SI_INFO(sih);
2301 if (BUSTYPE(sih->bustype) == SI_BUS)
2315 if (BUSTYPE(sih->bustype) == PCI_BUS) {
2328 si_osh(si_t *sih)
2332 sii = SI_INFO(sih);
2337 si_setosh(si_t *sih, osl_t *osh)
2341 sii = SI_INFO(sih);
2351 BCMATTACHFN(si_register_intr_callback)(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
2356 sii = SI_INFO(sih);
2368 BCMATTACHFN(si_deregister_intr_callback)(si_t *sih)
2372 sii = SI_INFO(sih);
2379 si_intflag(si_t *sih)
2381 si_info_t *sii = SI_INFO(sih);
2383 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2384 return sb_intflag(sih);
2385 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2395 si_flag(si_t *sih)
2397 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2398 return sb_flag(sih);
2399 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2400 return ai_flag(sih);
2401 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2402 return ub_flag(sih);
2410 si_flag_alt(si_t *sih)
2412 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2413 return ai_flag_alt(sih);
2421 si_setint(si_t *sih, int siflag)
2423 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2424 sb_setint(sih, siflag);
2425 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2426 ai_setint(sih, siflag);
2427 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2428 ub_setint(sih, siflag);
2434 si_coreid(si_t *sih)
2438 sii = SI_INFO(sih);
2443 si_coreidx(si_t *sih)
2447 sii = SI_INFO(sih);
2453 si_coreunit(si_t *sih)
2461 sii = SI_INFO(sih);
2467 coreid = si_coreid(sih);
2478 si_corevendor(si_t *sih)
2480 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2481 return sb_corevendor(sih);
2482 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2483 return ai_corevendor(sih);
2484 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2485 return ub_corevendor(sih);
2493 si_backplane64(si_t *sih)
2495 return ((sih->cccaps & CC_CAP_BKPLN64) != 0);
2499 si_corerev(si_t *sih)
2501 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2502 return sb_corerev(sih);
2503 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2504 return ai_corerev(sih);
2505 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2506 return ub_corerev(sih);
2516 si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
2522 sii = SI_INFO(sih);
2538 si_corelist(si_t *sih, uint coreid[])
2542 sii = SI_INFO(sih);
2550 si_wrapperregs(si_t *sih)
2554 sii = SI_INFO(sih);
2562 si_coreregs(si_t *sih)
2566 sii = SI_INFO(sih);
2578 si_setcore(si_t *sih, uint coreid, uint coreunit)
2582 idx = si_findcoreidx(sih, coreid, coreunit);
2586 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2587 return sb_setcoreidx(sih, idx);
2588 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2589 return ai_setcoreidx(sih, idx);
2590 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2591 return ub_setcoreidx(sih, idx);
2599 si_setcoreidx(si_t *sih, uint coreidx)
2601 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2602 return sb_setcoreidx(sih, coreidx);
2603 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2604 return ai_setcoreidx(sih, coreidx);
2605 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2606 return ub_setcoreidx(sih, coreidx);
2615 si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
2618 si_info_t *sii = SI_INFO(sih);
2628 else if (coreid == sih->buscoretype)
2633 cc = si_setcore(sih, coreid, 0);
2641 si_restore_core(si_t *sih, uint coreid, uint intr_val)
2645 sii = SI_INFO(sih);
2646 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
2649 si_setcoreidx(sih, coreid);
2654 si_numaddrspaces(si_t *sih)
2656 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2657 return sb_numaddrspaces(sih);
2658 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2659 return ai_numaddrspaces(sih);
2660 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2661 return ub_numaddrspaces(sih);
2669 si_addrspace(si_t *sih, uint asidx)
2671 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2672 return sb_addrspace(sih, asidx);
2673 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2674 return ai_addrspace(sih, asidx);
2675 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2676 return ub_addrspace(sih, asidx);
2684 si_addrspacesize(si_t *sih, uint asidx)
2686 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2687 return sb_addrspacesize(sih, asidx);
2688 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2689 return ai_addrspacesize(sih, asidx);
2690 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2691 return ub_addrspacesize(sih, asidx);
2699 si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
2702 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2703 ai_coreaddrspaceX(sih, asidx, addr, size);
2709 si_core_cflags(si_t *sih, uint32 mask, uint32 val)
2711 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2712 return sb_core_cflags(sih, mask, val);
2713 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2714 return ai_core_cflags(sih, mask, val);
2715 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2716 return ub_core_cflags(sih, mask, val);
2724 si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
2726 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2727 sb_core_cflags_wo(sih, mask, val);
2728 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2729 ai_core_cflags_wo(sih, mask, val);
2730 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2731 ub_core_cflags_wo(sih, mask, val);
2737 si_core_sflags(si_t *sih, uint32 mask, uint32 val)
2739 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2740 return sb_core_sflags(sih, mask, val);
2741 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2742 return ai_core_sflags(sih, mask, val);
2743 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2744 return ub_core_sflags(sih, mask, val);
2752 si_iscoreup(si_t *sih)
2754 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2755 return sb_iscoreup(sih);
2756 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2757 return ai_iscoreup(sih);
2758 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2759 return ub_iscoreup(sih);
2767 si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
2770 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2771 return (ai_wrap_reg(sih, offset, mask, val));
2776 si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
2778 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2779 return sb_corereg(sih, coreidx, regoff, mask, val);
2780 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2781 return ai_corereg(sih, coreidx, regoff, mask, val);
2782 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2783 return ub_corereg(sih, coreidx, regoff, mask, val);
2805 si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val)
2810 if (mask != 0 && sih->pmurev >= 22 &&
2812 pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) :
2815 while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING)
2819 return si_corereg(sih, idx, regoff, mask, val);
2832 si_corereg_addr(si_t *sih, uint coreidx, uint regoff)
2834 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2835 return sb_corereg_addr(sih, coreidx, regoff);
2836 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2837 return ai_corereg_addr(sih, coreidx, regoff);
2844 si_core_disable(si_t *sih, uint32 bits)
2846 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2847 sb_core_disable(sih, bits);
2848 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2849 ai_core_disable(sih, bits);
2850 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2851 ub_core_disable(sih, bits);
2855 si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
2857 if (CHIPTYPE(sih->socitype) == SOCI_SB)
2858 sb_core_reset(sih, bits, resetbits);
2859 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
2860 ai_core_reset(sih, bits, resetbits);
2861 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
2862 ub_core_reset(sih, bits, resetbits);
2867 si_corebist(si_t *sih)
2873 cflags = si_core_cflags(sih, 0, 0);
2876 si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC));
2879 SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000);
2881 if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR)
2885 si_core_cflags(sih, 0xffff, cflags);
2993 si_chip_hostif(si_t *sih)
2997 switch (CHIPID(sih->chip)) {
3008 if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB))
3017 if (CST4335_CHIPMODE_USB20D(sih->chipst))
3019 else if (CST4335_CHIPMODE_SDIOD(sih->chipst))
3026 if (CST4345_CHIPMODE_USB20D(sih->chipst) || CST4345_CHIPMODE_HSIC(sih->chipst))
3028 else if (CST4345_CHIPMODE_SDIOD(sih->chipst))
3030 else if (CST4345_CHIPMODE_PCIE(sih->chipst))
3043 if (CST4350_CHIPMODE_USB20D(sih->chipst) ||
3044 CST4350_CHIPMODE_HSIC20D(sih->chipst) ||
3045 CST4350_CHIPMODE_USB30D(sih->chipst) ||
3046 CST4350_CHIPMODE_USB30D_WL(sih->chipst) ||
3047 CST4350_CHIPMODE_HSIC30D(sih->chipst))
3049 else if (CST4350_CHIPMODE_SDIOD(sih->chipst))
3051 else if (CST4350_CHIPMODE_PCIE(sih->chipst))
3062 bool si_read_pmu_autopll(si_t *sih)
3065 sii = SI_INFO(sih);
3066 return (si_pmu_is_autoresetphyclk_disabled(sih, sii->osh));
3070 BCMINITFN(si_clock)(si_t *sih)
3079 if (BCM4707_CHIP(CHIPID(sih->chip))) {
3080 if (sih->chippkg == BCM4709_PKG_ID) {
3086 sii = SI_INFO(sih);
3088 if (PMUCTL_ENAB(sih)) {
3089 rate = si_pmu_si_clock(sih, sii->osh);
3094 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
3098 pll_type = sih->cccaps & CC_CAP_PLL_MASK;
3113 si_setcoreidx(sih, idx);
3122 BCMINITFN(si_ns_alp_clock)(si_t *sih)
3124 osl_t *osh = si_osh(sih);
3164 BCMINITFN(si_alp_clock)(si_t *sih)
3166 if (PMUCTL_ENAB(sih))
3167 return si_pmu_alp_clock(sih, si_osh(sih));
3168 else if (BCM4707_CHIP(CHIPID(sih->chip))) {
3169 return si_ns_alp_clock(sih);
3177 BCMINITFN(si_ilp_clock)(si_t *sih)
3179 if (PMUCTL_ENAB(sih))
3180 return si_pmu_ilp_clock(sih, si_osh(sih));
3187 si_watchdog(si_t *sih, uint ticks)
3191 if (PMUCTL_ENAB(sih)) {
3194 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) &&
3195 (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) {
3196 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), ~0, 0x2);
3197 si_setcore(sih, USB20D_CORE_ID, 0);
3198 si_core_disable(sih, 1);
3199 si_setcore(sih, CC_CORE_ID, 0);
3203 if (CHIPID(sih->chip) == BCM4706_CHIP_ID)
3206 nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
3220 pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
3222 if (!BCM4707_CHIP(CHIPID(sih->chip))) {
3224 si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC);
3230 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
3236 si_watchdog_ms(si_t *sih, uint32 ms)
3238 si_watchdog(sih, wd_msticks * ms);
3247 si_taclear(si_t *sih, bool details)
3250 if (CHIPTYPE(sih->socitype) == SOCI_SB)
3251 return sb_taclear(sih, details);
3252 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
3254 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
3266 BCMATTACHFN(si_d11_devid)(si_t *sih)
3268 si_info_t *sii = SI_INFO(sih);
3272 if (CHIPID(sih->chip) == BCM4328_CHIP_ID &&
3273 (sih->chippkg == BCM4328USBDUAL_PKG_ID || sih->chippkg == BCM4328SDIODUAL_PKG_ID)) {
3277 else if (CHIPID(sih->chip) == BCM4352_CHIP_ID) {
3279 } else if (CHIPID(sih->chip) == BCM4360_CHIP_ID) {
3281 } else if (BCM4350_CHIP(sih->chip)) {
3283 } else if ((CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
3284 (CHIPID(sih->chip) == BCM43462_CHIP_ID)) {
3290 if ((device = (uint16)si_getdevpathintvar(sih, rstr_devid)) != 0)
3298 else if (CHIPID(sih->chip) == BCM4712_CHIP_ID) {
3300 if (sih->chippkg == BCM4712SMALL_PKG_ID)
3313 BCMATTACHFN(si_corepciid)(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
3320 uint32 core = si_coreid(sih);
3327 switch (si_corevendor(sih)) {
3445 device = si_d11_devid(sih);
3467 si_dumpregs(si_t *sih, struct bcmstrbuf *b)
3469 si_info_t *sii = SI_INFO(sih);
3475 if (CHIPTYPE(sih->socitype) == SOCI_SB)
3476 sb_dumpregs(sih, b);
3477 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || (CHIPTYPE(sih->socitype) == SOCI_NAI))
3478 ai_dumpregs(sih, b);
3479 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS)
3480 ub_dumpregs(sih, b);
3484 si_setcoreidx(sih, origidx);
3580 BCMINITFN(si_clkctl_init)(si_t *sih)
3587 if (!CCCTL_ENAB(sih))
3590 sii = SI_INFO(sih);
3594 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
3601 if (sih->ccrev >= 10)
3610 si_setcoreidx(sih, origidx);
3615 BCMINITFN(si_clkctl_fast_pwrup_delay)(si_t *sih)
3617 si_info_t *sii = SI_INFO(sih);
3625 if (PMUCTL_ENAB(sih)) {
3627 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
3632 if (!CCCTL_ENAB(sih))
3640 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
3653 si_setcoreidx(sih, origidx);
3661 si_clkctl_xtal(si_t *sih, uint what, bool on)
3666 sii = SI_INFO(sih);
3668 switch (BUSTYPE(sih->bustype)) {
3744 si_clkctl_cc(si_t *sih, uint mode)
3748 sii = SI_INFO(sih);
3751 if (sih->ccrev < 6)
3865 BCMNMIATTACHFN(si_devpath)(si_t *sih, char *path, int size)
3875 switch (BUSTYPE(sih->bustype)) {
3878 slen = snprintf(path, (size_t)size, "sb/%u/", si_coreidx(sih));
3881 ASSERT((SI_INFO(sih))->osh != NULL);
3883 OSL_PCI_BUS((SI_INFO(sih))->osh),
3884 OSL_PCI_SLOT((SI_INFO(sih))->osh));
3906 BCMNMIATTACHFN(si_devpath_pcie)(si_t *sih, char *path, int size)
3914 ASSERT((SI_INFO(sih))->osh != NULL);
3916 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh),
3917 OSL_PCIE_BUS((SI_INFO(sih))->osh));
3923 BCMATTACHFN(si_coded_devpathvar)(si_t *sih, char *varname, int var_len, const char *name)
3934 if (BUSTYPE(sih->bustype) == PCI_BUS) {
3936 OSL_PCIE_DOMAIN((SI_INFO(sih))->osh),
3937 OSL_PCIE_BUS((SI_INFO(sih))->osh));
3942 if (si_devpath(sih, devpath, SI_DEVPATH_BUFSZ) == 0) {
3978 BCMATTACHFN(si_getdevpathvar)(si_t *sih, const char *name)
3983 si_devpathvar(sih, varname, sizeof(varname), name);
3988 if (BUSTYPE(sih->bustype) == PCI_BUS) {
3989 si_pcie_devpathvar(sih, varname, sizeof(varname), name);
3995 if (si_coded_devpathvar(sih, varname, sizeof(varname), name) == NULL)
4003 BCMATTACHFN(si_getdevpathintvar)(si_t *sih, const char *name)
4011 si_devpathvar(sih, varname, sizeof(varname), name);
4016 if (BUSTYPE(sih->bustype) == PCI_BUS) {
4017 si_pcie_devpathvar(sih, varname, sizeof(varname), name);
4023 if (si_coded_devpathvar(sih, varname, sizeof(varname), name) == NULL)
4032 si_getnvramflvar(si_t *sih, const char *name)
4045 BCMATTACHFN(si_devpathvar)(si_t *sih, char *var, int len, const char *name)
4052 if (si_devpath(sih, var, len) == 0) {
4065 BCMATTACHFN(si_pcie_devpathvar)(si_t *sih, char *var, int len, const char *name)
4072 if (si_devpath_pcie(sih, var, len) == 0) {
4085 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val)
4090 sii = SI_INFO(sih);
4104 si_dump_pmu(si_t *sih, void *arg)
4112 pmu_var->pmu_control = si_ccreg(sih, PMU_CTL, 0, 0);
4113 pmu_var->pmu_capabilities = si_ccreg(sih, PMU_CAP, 0, 0);
4114 pmu_var->pmu_status = si_ccreg(sih, PMU_ST, 0, 0);
4115 pmu_var->res_state = si_ccreg(sih, PMU_RES_STATE, 0, 0);
4116 pmu_var->res_pending = si_ccreg(sih, PMU_RES_PENDING, 0, 0);
4117 pmu_var->pmu_timer1 = si_ccreg(sih, PMU_TIMER, 0, 0);
4118 pmu_var->min_res_mask = si_ccreg(sih, MINRESMASKREG, 0, 0);
4119 pmu_var->max_res_mask = si_ccreg(sih, MAXRESMASKREG, 0, 0);
4123 pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0);
4128 pmu_var->pmu_regcontrol[i] = si_pmu_regcontrol(sih, i, 0, 0);
4133 pmu_var->pmu_pllcontrol[i] = si_pmu_pllcontrol(sih, i, 0, 0);
4138 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i);
4139 pmu_var->pmu_rsrc_up_down_timer[i] = si_corereg(sih, SI_CC_IDX,
4145 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i);
4146 pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0);
4151 si_pmu_keep_on(si_t *sih, int32 int_val)
4155 sii = SI_INFO(sih);
4156 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
4174 si_pmu_keep_on_get(si_t *sih)
4179 sii = SI_INFO(sih);
4180 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
4199 si_power_island_set(si_t *sih, uint32 int_val)
4224 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x003c0000, j);
4233 si_power_island_get(si_t *sih)
4241 reg_val = si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0, 0);
4260 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type)
4264 sii = SI_INFO(sih);
4275 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val)
4279 sii = SI_INFO(sih);
4309 si_pci_pmeen(si_t *sih)
4311 pcicore_pmeen(SI_INFO(sih)->pch);
4316 si_pci_pmestat(si_t *sih)
4318 return pcicore_pmestat(SI_INFO(sih)->pch);
4323 si_pci_pmeclr(si_t *sih)
4325 pcicore_pmeclr(SI_INFO(sih)->pch);
4329 si_pci_pmestatclr(si_t *sih)
4331 pcicore_pmestatclr(SI_INFO(sih)->pch);
4336 si_pcmcia_init(si_t *sih)
4338 si_info_t *sii = SI_INFO(sih);
4350 BCMATTACHFN(si_pci_war16165)(si_t *sih)
4352 si_info_t *sii = SI_INFO(sih);
4354 return (PCI(sii) && (sih->buscorerev <= 10));
4364 si_pcie_war_ovr_update(si_t *sih, uint8 aspm)
4366 si_info_t *sii = SI_INFO(sih);
4375 si_pcie_power_save_enable(si_t *sih, bool enable)
4377 si_info_t *sii = SI_INFO(sih);
4386 si_pcie_set_maxpayload_size(si_t *sih, uint16 size)
4388 si_info_t *sii = SI_INFO(sih);
4397 si_pcie_get_maxpayload_size(si_t *sih)
4399 si_info_t *sii = SI_INFO(sih);
4408 si_pcie_set_request_size(si_t *sih, uint16 size)
4410 si_info_t *sii = SI_INFO(sih);
4419 si_pcie_get_request_size(si_t *sih)
4421 si_info_t *sii = SI_INFO(sih);
4431 si_pcie_get_ssid(si_t *sih)
4433 si_info_t *sii = SI_INFO(sih);
4442 si_pcie_get_bar0(si_t *sih)
4444 si_info_t *sii = SI_INFO(sih);
4453 si_pcie_configspace_cache(si_t *sih)
4455 si_info_t *sii = SI_INFO(sih);
4464 si_pcie_configspace_restore(si_t *sih)
4466 si_info_t *sii = SI_INFO(sih);
4475 si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size)
4477 si_info_t *sii = SI_INFO(sih);
4487 si_chippkg_set(si_t *sih, uint val)
4489 si_info_t *sii = SI_INFO(sih);
4495 si_pcie_hw_L1SS_war(si_t *sih)
4497 si_info_t *sii = SI_INFO(sih);
4504 BCMINITFN(si_pci_up)(si_t *sih)
4509 if (BUSTYPE(sih->bustype) != PCI_BUS)
4512 sii = SI_INFO(sih);
4519 if (((CHIPID(sih->chip) == BCM4311_CHIP_ID) && (CHIPREV(sih->chiprev) == 2)) ||
4520 (CHIPID(sih->chip) == BCM4312_CHIP_ID))
4528 BCMUNINITFN(si_pci_sleep)(si_t *sih)
4532 pcicore_sleep(SI_INFO(sih)->pch);
4537 BCMINITFN(si_pci_down)(si_t *sih)
4539 si_info_t *sii = SI_INFO(sih);
4542 if (BUSTYPE(sih->bustype) != PCI_BUS)
4557 BCMATTACHFN(si_pci_setup)(si_t *sih, uint coremask)
4559 si_info_t *sii = SI_INFO(sih);
4575 siflag = si_flag(sih);
4578 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx);
4596 si_setint(sih, siflag);
4609 si_setcoreidx(sih, idx);
4614 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val)
4616 si_info_t *sii = SI_INFO(sih);
4625 si_pcielcreg(si_t *sih, uint32 mask, uint32 val)
4627 si_info_t *sii = SI_INFO(sih);
4636 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val)
4638 si_info_t *sii = SI_INFO(sih);
4647 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val)
4651 sii = SI_INFO(sih);
4660 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val)
4662 si_info_t *sii = SI_INFO(sih);
4671 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val)
4673 si_info_t *sii = SI_INFO(sih);
4682 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val)
4684 si_info_t *sii = SI_INFO(sih);
4693 si_pcie_set_error_injection(si_t *sih, uint32 mode)
4695 si_info_t *sii = SI_INFO(sih);
4704 si_pcie_set_L1substate(si_t *sih, uint32 substate)
4708 sii = SI_INFO(sih);
4715 si_pcie_get_L1substate(si_t *sih)
4719 sii = SI_INFO(sih);
4729 si_pcie_readreg(void *sih, uint addrtype, uint offset)
4731 return pcie_readreg(sih, (sbpcieregs_t *)PCIEREGS(((si_info_t *)sih)),
4737 si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val)
4739 return pcie_writereg(sih, (sbpcieregs_t *)PCIEREGS(((si_info_t *)sih)),
4751 si_pci_fixcfg(si_t *sih)
4759 si_info_t *sii = SI_INFO(sih);
4804 si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b)
4806 si_info_t *sii = SI_INFO(sih);
4819 si_gpiosetcore(si_t *sih)
4821 return (si_setcoreidx(sih, SI_CC_IDX));
4831 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority)
4841 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
4848 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4853 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority)
4863 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
4870 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4875 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority)
4885 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
4892 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4897 si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority)
4902 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
4903 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
4928 si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority)
4933 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) {
4934 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority));
4955 si_gpioin(si_t *sih)
4960 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
4965 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority)
4970 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
4977 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4982 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
4987 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
4994 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4999 si_gpioled(si_t *sih, uint32 mask, uint32 val)
5001 if (sih->ccrev < 16)
5005 return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
5010 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
5012 if (sih->ccrev < 16)
5015 return (si_corereg(sih, SI_CC_IDX,
5020 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
5024 if (sih->ccrev < 20)
5028 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
5032 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
5036 if (sih->ccrev < 11)
5048 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
5052 BCMATTACHFN(si_gpio_handler_register)(si_t *sih, uint32 event,
5061 sii = SI_INFO(sih);
5062 if (sih->ccrev < 11)
5081 BCMATTACHFN(si_gpio_handler_unregister)(si_t *sih, void *gpioh)
5086 if (sih->ccrev < 11)
5089 sii = SI_INFO(sih);
5113 si_gpio_handler_process(si_t *sih)
5115 si_info_t *sii = SI_INFO(sih);
5117 uint32 level = si_gpioin(sih);
5118 uint32 levelp = si_gpiointpolarity(sih, 0, 0, 0);
5119 uint32 edge = si_gpioevent(sih, GPIO_REGEVT, 0, 0);
5120 uint32 edgep = si_gpioevent(sih, GPIO_REGEVT_INTPOL, 0, 0);
5133 si_gpioevent(sih, GPIO_REGEVT, edge, edge); /* clear edge-trigger status */
5137 BCMATTACHFN(si_gpio_int_enable)(si_t *sih, bool enable)
5141 if (sih->ccrev < 11)
5145 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
5165 si_socdevram(si_t *sih, bool set, uint8 *enable, uint8 *protect, uint8 *remap)
5167 si_info_t *sii = SI_INFO(sih);
5176 origidx = si_coreidx(sih);
5182 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5186 if (!(wasup = si_iscoreup(sih)))
5187 si_core_reset(sih, 0, 0);
5189 corerev = si_corerev(sih);
5230 si_core_disable(sih, 0);
5231 si_setcoreidx(sih, origidx);
5238 si_socdevram_remap_isenb(si_t *sih)
5240 si_info_t *sii = SI_INFO(sih);
5253 origidx = si_coreidx(sih);
5256 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5260 if (!(wasup = si_iscoreup(sih)))
5261 si_core_reset(sih, 0, 0);
5263 corerev = si_corerev(sih);
5280 si_core_disable(sih, 0);
5281 si_setcoreidx(sih, origidx);
5289 si_socdevram_pkg(si_t *sih)
5291 if (si_socdevram_size(sih) > 0)
5298 si_socdevram_size(si_t *sih)
5300 si_info_t *sii = SI_INFO(sih);
5310 origidx = si_coreidx(sih);
5313 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5317 if (!(wasup = si_iscoreup(sih)))
5318 si_core_reset(sih, 0, 0);
5320 corerev = si_corerev(sih);
5334 si_core_disable(sih, 0);
5335 si_setcoreidx(sih, origidx);
5344 si_socdevram_remap_size(si_t *sih)
5346 si_info_t *sii = SI_INFO(sih);
5360 origidx = si_coreidx(sih);
5363 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5367 if (!(wasup = si_iscoreup(sih)))
5368 si_core_reset(sih, 0, 0);
5370 corerev = si_corerev(sih);
5398 si_core_disable(sih, 0);
5399 si_setcoreidx(sih, origidx);
5409 si_socram_size(si_t *sih)
5411 si_info_t *sii = SI_INFO(sih);
5423 origidx = si_coreidx(sih);
5426 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5430 if (!(wasup = si_iscoreup(sih)))
5431 si_core_reset(sih, 0, 0);
5432 corerev = si_corerev(sih);
5459 si_core_disable(sih, 0);
5460 si_setcoreidx(sih, origidx);
5472 si_tcm_size(si_t *sih)
5490 sii = SI_INFO(sih);
5494 origidx = si_coreidx(sih);
5497 if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0)))
5503 if (!(wasup = si_iscoreup(sih)))
5504 si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT);
5524 si_core_disable(sih, 0);
5525 si_setcoreidx(sih, origidx);
5534 si_has_flops(si_t *sih)
5539 origidx = si_coreidx(sih);
5540 if (si_setcore(sih, ARMCR4_CORE_ID, 0)) {
5541 cr4_rev = si_corerev(sih);
5542 si_setcoreidx(sih, origidx);
5552 si_socram_srmem_size(si_t *sih)
5564 if ((CHIPID(sih->chip) == BCM4334_CHIP_ID) && (CHIPREV(sih->chiprev) < 2)) {
5568 sii = SI_INFO(sih);
5572 origidx = si_coreidx(sih);
5575 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0)))
5579 if (!(wasup = si_iscoreup(sih)))
5580 si_core_reset(sih, 0, 0);
5581 corerev = si_corerev(sih);
5597 si_core_disable(sih, 0);
5598 si_setcoreidx(sih, origidx);
5607 #define NOTIFY_BT_FM_DISABLE(sih, val) \
5608 si_eci_notify_bt((sih), ECI_OUT_FM_DISABLE_MASK(sih->ccrev), \
5609 ((val) << ECI_OUT_FM_DISABLE_SHIFT(sih->ccrev)), FALSE)
5613 BCMINITFN(si_query_FMDisabled_from_OTP)(si_t *sih, uint16 *FMDisabled)
5622 switch (CHIPID(sih->chip)) {
5624 if (CHIPREV(sih->chiprev) >= 6)
5633 if (!(wasup = si_is_otp_powered(sih))) {
5634 si_otp_power(sih, TRUE, &min_res_mask);
5637 if ((oh = otp_init(sih)) != NULL)
5643 si_otp_power(sih, FALSE, &min_res_mask);
5651 si_eci(si_t *sih)
5653 return (!!(sih->cccaps & CC_CAP_ECI));
5657 si_seci(si_t *sih)
5659 return (sih->cccaps_ext & CC_CAP_EXT_SECI_PRESENT);
5663 si_gci(si_t *sih)
5665 return (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT);
5670 BCMINITFN(si_eci_init)(si_t *sih)
5679 if (!(sih->cccaps & CC_CAP_ECI))
5682 sii = SI_INFO(sih);
5686 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
5693 if (sih->ccrev < 35) {
5704 if (sih->ccrev < 35) {
5715 if (sih->ccrev < 35) {
5727 si_setcoreidx(sih, origidx);
5730 if (!si_query_FMDisabled_from_OTP(sih, &FMDisabled)) {
5732 NOTIFY_BT_FM_DISABLE(sih, 1);
5741 si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool interrupt)
5745 if ((sih->cccaps & CC_CAP_ECI) ||
5746 (si_seci(sih)))
5751 si_corereg(sih, SI_CC_IDX,
5752 (sih->ccrev < 35 ?
5757 if (sih->ccrev >= 35) {
5773 si_corereg(sih, SI_CC_IDX, offset, mask, val);
5777 si_corereg(sih, SI_CC_IDX,
5778 (sih->ccrev < 35 ?
5783 else if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)
5788 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_output[1]), mask, val);
5795 si_seci_clkreq(si_t *sih, bool enable)
5801 if (!si_seci(sih))
5811 si_corereg(sih, SI_CC_IDX, offset, CLKCTL_STS_SECI_CLK_REQ, val);
5816 SPINWAIT(!(si_corereg(sih, 0, offset, 0, 0) & CLKCTL_STS_SECI_CLK_AVAIL),
5819 clk_ctl_st = si_corereg(sih, 0, offset, 0, 0);
5829 BCMINITFN(si_seci_down)(si_t *sih)
5837 if (!si_seci(sih))
5840 sii = SI_INFO(sih);
5845 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
5851 if (CHIPID(sih->chip) == BCM4331_CHIP_ID) {
5871 si_seci_clkreq(sih, FALSE);
5875 si_setcoreidx(sih, origidx);
5879 si_seci_upd(si_t *sih, bool enable)
5888 if (!si_seci(sih))
5891 sii = SI_INFO(sih);
5896 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL)
5904 if ((CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
5905 (CHIPID(sih->chip) == BCM4352_CHIP_ID) ||
5906 (CHIPID(sih->chip) == BCM4360_CHIP_ID)) {
5909 if (CHIPID(sih->chip) == BCM4331_CHIP_ID) {
5937 si_setcoreidx(sih, origidx);
5944 BCMINITFN(si_seci_init)(si_t *sih, uint8 seci_mode)
5955 if (sih->ccrev < 35)
5958 if (!si_seci(sih))
5964 sii = SI_INFO(sih);
5968 if ((ptr = si_setcore(sih, CC_CORE_ID, 0)) == NULL)
5977 if (CHIPID(sih->chip) == BCM43236_CHIP_ID ||
5978 CHIPID(sih->chip) == BCM4331_CHIP_ID) {
5985 if (CHIPID(sih->chip) == BCM43143_CHIP_ID) {
6001 if ((CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
6002 (CHIPID(sih->chip) == BCM43143_CHIP_ID)) {
6010 si_seci_clkreq(sih, TRUE);
6039 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFF); /* 4MBaud */
6041 if ((CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
6042 (CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
6043 (CHIPID(sih->chip) == BCM43143_CHIP_ID)) {
6046 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44);
6048 else if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
6049 (CHIPID(sih->chip) == BCM43460_CHIP_ID) ||
6050 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
6051 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
6052 (CHIPID(sih->chip) == BCM43526_CHIP_ID) ||
6053 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) {
6056 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFE);
6058 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44);
6062 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x22);
6067 si_corereg(sih, SI_CC_IDX, offset, 0xFF,
6070 si_corereg(sih, SI_CC_IDX, offset,
6075 si_corereg(sih, SI_CC_IDX, offset, ALLONES_32, ECI_MACCTRLLO_BITS);
6077 si_corereg(sih, SI_CC_IDX, offset, 0xFFFF, ECI_MACCTRLHI_BITS);
6093 si_setcoreidx(sih, origidx);
6099 BCMINITFN(si_gci_init)(si_t *sih)
6102 si_info_t *sii = SI_INFO(sih);
6105 if (sih->cccaps_ext & CC_CAP_EXT_GCI_PRESENT)
6107 si_gci_reset(sih);
6111 si_gci_direct(sih, OFFSETOF(chipcregs_t, gci_control_1),
6114 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) &&
6115 (CHIPREV(sih->ccrev) == 46))
6116 si_gci_chipcontrol(sih, 0, ~0, 0x11111111);
6119 hndgci_init(sih, sii->osh, HND_GCI_PLAIN_UART_MODE,
6129 si_btcgpiowar(si_t *sih)
6139 if (!(sih->cccaps & CC_CAP_UARTGPIO))
6142 sii = SI_INFO(sih);
6147 origidx = si_coreidx(sih);
6149 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6155 si_setcoreidx(sih, origidx);
6161 si_chipcontrl_btshd0_4331(si_t *sih, bool on)
6163 si_info_t *sii = SI_INFO(sih);
6171 origidx = si_coreidx(sih);
6173 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6188 si_setcoreidx(sih, origidx);
6194 si_chipcontrl_restore(si_t *sih, uint32 val)
6196 si_info_t *sii = SI_INFO(sih);
6198 uint origidx = si_coreidx(sih);
6200 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6202 si_setcoreidx(sih, origidx);
6206 si_chipcontrl_read(si_t *sih)
6208 si_info_t *sii = SI_INFO(sih);
6210 uint origidx = si_coreidx(sih);
6213 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6215 si_setcoreidx(sih, origidx);
6220 si_chipcontrl_epa4331(si_t *sih, bool on)
6222 si_info_t *sii = SI_INFO(sih);
6224 uint origidx = si_coreidx(sih);
6227 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6231 if (sih->chippkg == 9 || sih->chippkg == 0xb) {
6237 if (sih->chiprev > 0) {
6249 si_setcoreidx(sih, origidx);
6254 si_chipcontrl_srom4360(si_t *sih, bool on)
6256 si_info_t *sii = SI_INFO(sih);
6258 uint origidx = si_coreidx(sih);
6261 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6275 si_setcoreidx(sih, origidx);
6279 si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl)
6287 sel_chip = (CHIPID(sih->chip) == BCM4331_CHIP_ID) ||
6288 (CHIPID(sih->chip) == BCM43431_CHIP_ID);
6289 sel_chip &= ((sih->chippkg == 9 || sih->chippkg == 0xb));
6294 sii = SI_INFO(sih);
6295 origidx = si_coreidx(sih);
6297 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6308 si_setcoreidx(sih, origidx);
6313 si_pll_reset(si_t *sih)
6318 si_info_t *sii = SI_INFO(sih);
6321 err = si_pll_minresmask_reset(sih, sii->osh);
6328 si_epa_4313war(si_t *sih)
6330 si_info_t *sii = SI_INFO(sih);
6332 uint origidx = si_coreidx(sih);
6334 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6340 si_setcoreidx(sih, origidx);
6344 si_clk_pmu_htavail_set(si_t *sih, bool set_clear)
6346 si_info_t *sii = SI_INFO(sih);
6348 si_pmu_minresmask_htavail_set(sih, sii->osh, set_clear);
6353 si_pmu_synth_pwrsw_4313_war(si_t *sih)
6355 si_info_t *sii = SI_INFO(sih);
6356 if (!(*(uint32 *)PMUREG(sih, min_res_mask) & PMURES_BIT(RES4313_SYNTH_PWRSW_RSRC)))
6357 OR_REG(sii->osh, PMUREG(sih, min_res_mask), PMURES_BIT(RES4313_SYNTH_PWRSW_RSRC));
6362 si_btcombo_p250_4313_war(si_t *sih)
6364 si_info_t *sii = SI_INFO(sih);
6366 uint origidx = si_coreidx(sih);
6368 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6375 si_setcoreidx(sih, origidx);
6378 si_btc_enable_chipcontrol(si_t *sih)
6380 si_info_t *sii = SI_INFO(sih);
6382 uint origidx = si_coreidx(sih);
6384 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6390 si_setcoreidx(sih, origidx);
6393 si_btcombo_43228_war(si_t *sih)
6395 si_info_t *sii = SI_INFO(sih);
6397 uint origidx = si_coreidx(sih);
6399 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
6404 si_setcoreidx(sih, origidx);
6409 si_deviceremoved(si_t *sih)
6413 switch (BUSTYPE(sih->bustype)) {
6415 ASSERT(SI_INFO(sih)->osh != NULL);
6416 w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32));
6425 si_is_sprom_available(si_t *sih)
6427 if (sih->ccrev >= 31) {
6433 if ((sih->cccaps & CC_CAP_SROM) == 0)
6436 sii = SI_INFO(sih);
6438 cc = si_setcoreidx(sih, SI_CC_IDX);
6441 si_setcoreidx(sih, origidx);
6445 switch (CHIPID(sih->chip)) {
6447 return ((sih->chipst & CST4312_SPROM_OTP_SEL_MASK) != CST4312_OTP_SEL);
6449 return (sih->chipst & CST4325_SPROM_SEL) != 0;
6454 spromotp = (sih->chipst & CST4322_SPROM_OTP_SEL_MASK) >>
6459 return (sih->chipst & CST4329_SPROM_SEL) != 0;
6461 return (sih->chipst & CST4315_SPROM_SEL) != 0;
6463 return (sih->chipst & CST4319_SPROM_SEL) != 0;
6466 return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
6468 return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
6470 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
6473 return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
6475 return ((sih->chipst & CST43239_SPROM_MASK) &&
6476 !(sih->chipst & CST43239_SFLASH_MASK));
6479 return ((sih->chipst & CST4324_SPROM_MASK) &&
6480 !(sih->chipst & CST4324_SFLASH_MASK));
6483 return ((sih->chipst & CST4335_SPROM_MASK) &&
6484 !(sih->chipst & CST4335_SFLASH_MASK));
6494 return (sih->chipst & CST4350_SPROM_PRESENT) != 0;
6497 return (sih->chipst & CST43602_SPROM_PRESENT) != 0;
6503 return (sih->chipst & CST43228_OTP_PRESENT) != CST43228_OTP_PRESENT;
6510 si_is_otp_disabled(si_t *sih)
6512 switch (CHIPID(sih->chip)) {
6514 return (sih->chipst & CST4325_SPROM_OTP_SEL_MASK) == CST4325_OTP_PWRDN;
6519 return (((sih->chipst & CST4322_SPROM_OTP_SEL_MASK) >>
6523 return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) == CST4329_OTP_PWRDN;
6525 return (sih->chipst & CST4315_SPROM_OTP_SEL_MASK) == CST4315_OTP_PWRDN;
6527 return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) == CST4319_OTP_PWRDN;
6530 return ((sih->chipst & CST4336_OTP_PRESENT) == 0);
6532 return ((sih->chipst & CST4330_OTP_PRESENT) == 0);
6536 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
6538 return (sih->chipst & CST4331_OTP_PRESENT) != CST4331_OTP_PRESENT;
6541 return (sih->chipst & CST43602_SPROM_PRESENT) != 0;
6580 si_is_otp_powered(si_t *sih)
6582 if (PMUCTL_ENAB(sih))
6583 return si_pmu_is_otp_powered(sih, si_osh(sih));
6588 si_otp_power(si_t *sih, bool on, uint32* min_res_mask)
6590 if (PMUCTL_ENAB(sih))
6591 si_pmu_otp_power(sih, si_osh(sih), on, min_res_mask);
6597 si_is_sprom_enabled(si_t *sih)
6599 BCMATTACHFN(si_is_sprom_enabled)(si_t *sih)
6602 if (PMUCTL_ENAB(sih))
6603 return si_pmu_is_sprom_enabled(sih, si_osh(sih));
6609 si_sprom_enable(si_t *sih, bool enable)
6611 BCMATTACHFN(si_sprom_enable)(si_t *sih, bool enable)
6614 if (PMUCTL_ENAB(sih))
6615 si_pmu_sprom_enable(sih, si_osh(sih), enable);
6620 si_cis_source(si_t *sih)
6627 if (BUSTYPE(sih->bustype) == PCI_BUS && !BCM4350_CHIP(sih->chip))
6630 switch (CHIPID(sih->chip)) {
6632 return ((sih->chipst & CST4325_SPROM_OTP_SEL_MASK) >= ARRAYSIZE(cis_sel)) ?
6633 CIS_DEFAULT : cis_sel[(sih->chipst & CST4325_SPROM_OTP_SEL_MASK)];
6636 uint8 strap = (sih->chipst & CST4322_SPROM_OTP_SEL_MASK) >>
6645 uint8 strap = (sih->chipst & CST43236_OTP_SEL_MASK) >>
6651 return ((sih->chipst & CST4329_SPROM_OTP_SEL_MASK) >= ARRAYSIZE(cis_sel)) ?
6652 CIS_DEFAULT : cis_sel[(sih->chipst & CST4329_SPROM_OTP_SEL_MASK)];
6656 return ((sih->chipst & CST4315_SPROM_OTP_SEL_MASK) >= ARRAYSIZE(cis_sel)) ?
6657 CIS_DEFAULT : cis_sel[(sih->chipst & CST4315_SPROM_OTP_SEL_MASK)];
6660 uint cis_sel4319 = ((sih->chipst & CST4319_SPROM_OTP_SEL_MASK) >>
6666 if (sih->chipst & CST4336_SPROM_PRESENT)
6668 if (sih->chipst & CST4336_OTP_PRESENT)
6673 if (sih->chipst & CST4330_SPROM_PRESENT)
6675 if (sih->chipst & CST4330_OTP_PRESENT)
6681 if (sih->chipst & CST4334_SPROM_PRESENT)
6683 if (sih->chipst & CST4334_OTP_PRESENT)
6688 if ((sih->chipst & CST43239_SPROM_MASK) && !(sih->chipst & CST43239_SFLASH_MASK))
6694 if ((sih->chipst & CST4324_SPROM_MASK) && !(sih->chipst & CST4324_SFLASH_MASK))
6701 if ((sih->chipst & CST4335_SPROM_MASK) && !(sih->chipst & CST4335_SFLASH_MASK))
6715 if (sih->chipst & CST4350_SPROM_PRESENT)
6720 uint8 strap = (sih->chipst & CST43237_OTP_SEL_MASK) >>
6736 if ((sih->chipst & CST4360_OTP_ENABLED))
6742 if (sih->chipst & CST43602_SPROM_PRESENT) {
6754 BCMINITFN(si_otp_fabid)(si_t *sih, uint16 *fabid, bool rw)
6760 switch (CHIPID(sih->chip)) {
6763 if (sih->chiprev >= 3) {
6788 error = otp_read_word(sih, offset, &data);
6795 error = otp_write_word(sih, offset, data);
6802 uint16 BCMATTACHFN(si_fabid)(si_t *sih)
6807 switch (CHIPID(sih->chip)) {
6811 if (si_otp_fabid(sih, &fabid, TRUE) != BCME_OK)
6818 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
6843 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, fabid), 0, 0);
6854 uint32 BCMATTACHFN(si_get_sromctl)(si_t *sih)
6857 uint origidx = si_coreidx(sih);
6859 osl_t *osh = si_osh(sih);
6861 cc = si_setcoreidx(sih, SI_CC_IDX);
6867 si_setcoreidx(sih, origidx);
6871 int BCMATTACHFN(si_set_sromctl)(si_t *sih, uint32 value)
6874 uint origidx = si_coreidx(sih);
6875 osl_t *osh = si_osh(sih);
6877 cc = si_setcoreidx(sih, SI_CC_IDX);
6881 if (si_corerev(sih) < 32)
6887 si_setcoreidx(sih, origidx);
6893 si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val)
6897 si_info_t *sii = SI_INFO(sih);
6899 origidx = si_coreidx(sih);
6902 si_setcoreidx(sih, coreidx);
6904 ret_val = si_wrapperreg(sih, offset, mask, val);
6907 si_setcoreidx(sih, origidx);
6918 si_update_masks(si_t *sih)
6920 si_info_t *sii = SI_INFO(sih);
6922 switch (CHIPID(sih->chip)) {
6934 if (PMUCTL_ENAB(sih))
6935 si_pmu_res_minmax_update(sih, sii->osh);
6939 if (PMUCTL_ENAB(sih))
6940 si_pmu_res_minmax_update(sih, sii->osh);
6941 si_ccreg(sih, PMUREG_RESREQ_MASK, ~0, 0x7ffbfff);
6943 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x01000000, 0x01000000);
6945 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x10, 0x10);
6948 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0xf0000, 0x10000);
6951 if (PMUCTL_ENAB(sih))
6952 si_pmu_res_minmax_update(sih, sii->osh);
6954 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x10, 0x10);
6957 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x80, 0);
6960 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0xf0000, 0x10000);
6963 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0xff000000, 0x0c000000);
6964 si_pmu_pllupd(sih);
6974 si_force_islanding(si_t *sih, bool enable)
6976 switch (CHIPID(sih->chip)) {
6982 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x1c0000, 0x0);
6985 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x100000, 0x100000);
6989 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x3c0000, 0x3c0000);
7005 si_pmu_res_req_timer_clr(si_t *sih)
7010 if (CHIPID(sih->chip) != BCM4328_CHIP_ID)
7013 pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0);
7015 return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0);
7021 si_pmu_rfldo(si_t *sih, bool on)
7023 switch (CHIPID(sih->chip)) {
7029 si_pmu_regcontrol(sih, 0, RCTRL4360_RFLDO_PWR_DOWN,
7040 si_pcie_set_ctrlreg(si_t *sih, uint32 mask, uint32 val)
7042 si_info_t *sii = SI_INFO(sih);
7048 if (((CHIPID(sih->chip) != BCM4335_CHIP_ID) || (BUSTYPE(sih->bustype) != PCI_BUS)))
7055 si_pcie_survive_perst(si_t *sih, uint32 mask, uint32 val)
7059 sii = SI_INFO(sih);
7068 si_watchdog_reset(si_t *sih)
7070 si_info_t *sii = SI_INFO(sih);
7074 W_REG(sii->osh, PMUREG(sih, pmuwatchdog), 2);
7083 si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 sperst_val)
7086 if (BUSTYPE(sih->bustype) != PCI_BUS)
7089 if ((CHIPID(sih->chip) != BCM4360_CHIP_ID && CHIPID(sih->chip) != BCM4352_CHIP_ID) ||
7090 (CHIPREV(sih->chiprev) >= 4))
7094 si_info_t *sii = SI_INFO(sih);
7100 si_watchdog_reset(sih);
7111 si_pcie_survive_perst(sih, sperst_mask, sperst_val);
7117 si_pcie_ltr_war(si_t *sih)
7119 si_info_t *sii = SI_INFO(sih);
7122 pcie_ltr_war(sii->pch, si_pcieltrenable(sih, 0, 0));
7126 si_pcie_hw_LTR_war(si_t *sih)
7128 si_info_t *sii = SI_INFO(sih);
7135 si_pciedev_reg_pm_clk_period(si_t *sih)
7137 si_info_t *sii = SI_INFO(sih);
7144 si_pciedev_crwlpciegen2(si_t *sih)
7146 si_info_t *sii = SI_INFO(sih);
7153 si_pcie_prep_D3(si_t *sih, bool enter_D3)
7155 si_info_t *sii = SI_INFO(sih);
7163 si_corereg_ifup(si_t *sih, uint core_id, uint regoff, uint mask, uint val)
7170 origidx = si_coreidx(sih);
7171 regs = si_setcore(sih, core_id, 0);
7175 coreidx = si_coreidx(sih);
7177 isup = si_iscoreup(sih);
7179 ret_val = si_corereg(sih, coreidx, regoff, mask, val);
7185 si_setcoreidx(sih, origidx);
7191 si_lowpwr_opt(si_t *sih)
7199 if (CHIPID(sih->chip) == BCM4335_CHIP_ID || CHIPID(sih->chip) == BCM4345_CHIP_ID ||
7200 BCM4350_CHIP(sih->chip) || CHIPID(sih->chip) == BCM43602_CHIP_ID ||
7201 CHIPID(sih->chip) == BCM43462_CHIP_ID) {
7202 uint hosti = si_chip_hostif(sih);
7203 uint origidx = si_coreidx(sih);
7207 regs = si_setcore(sih, CC_CORE_ID, 0);
7214 if (hosti != CHIP_HOSTIF_USBMODE && CHIPID(sih->chip) != BCM43602_CHIP_ID &&
7215 CHIPID(sih->chip) != BCM43462_CHIP_ID) {
7216 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << USBAPP_CLK_BIT), 0);
7220 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << PCIE_CLK_BIT), 0);
7225 switch (CHIPID(sih->chip)) {
7228 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, PMU43602_CC3_ARMCR4_DBG_CLK,
7233 uint32 tapsel = si_corereg(sih, SI_CC_IDX,
7237 si_pmu_chipcontrol(sih, PMU_CHIPCTL5,
7243 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT), 0);
7251 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
7255 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL0, mask, val);
7256 si_pmu_pllupd(sih);
7257 } else if (BCM4350_CHIP(sih->chip)) {
7267 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL0, mask, val);
7268 si_pmu_pllupd(sih);
7269 } else if ((CHIPID(sih->chip) == BCM43602_CHIP_ID ||
7270 CHIPID(sih->chip) == BCM43462_CHIP_ID)) {
7274 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL4, ~0, val);
7275 si_pmu_pllupd(sih);
7276 si_pmu_chipcontrol(sih, PMU_CHIPCTL2,
7283 if ((CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
7284 (CHIPID(sih->chip) == BCM4335_CHIP_ID && CHIPREV(sih->chiprev) >= 2) ||
7285 (CHIPID(sih->chip) == BCM4356_CHIP_ID) ||
7286 (CHIPID(sih->chip) == BCM4354_CHIP_ID) ||
7287 (CHIPID(sih->chip) == BCM4350_CHIP_ID && CHIPREV(sih->chiprev) >= 3)) {
7294 si_corereg_ifup(sih, D11_CORE_ID, SI_PWR_CTL_ST, mask, val);
7298 si_corereg_ifup(sih, ARMCR4_CORE_ID, SI_PWR_CTL_ST, mask, val);
7303 si_corereg_ifup(sih, SDIOD_CORE_ID, SI_PWR_CTL_ST, mask, val);
7306 si_corereg_ifup(sih, USB20D_CORE_ID, SI_PWR_CTL_ST, mask, val);
7309 si_corereg_ifup(sih, PCIE2_CORE_ID, SI_PWR_CTL_ST, mask, val);
7315 si_corereg_ifup(sih, CC_CORE_ID, 0xc0c, mask, val);
7318 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID && CHIPREV(sih->chiprev) >= 2) ||
7324 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, mask, val);
7332 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, PLL_DIV2_MASK, PLL_DIV2_DIS_OP);
7336 si_setcoreidx(sih, origidx);
7342 si_clear_backplane_to(si_t *sih)
7344 ai_clear_backplane_to(sih);
7352 si_get_uart_clock(si_t *sih, osl_t *osh, chipcregs_t *cc)
7356 rev = sih->ccrev;
7357 cap = sih->cccaps;
7360 if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
7367 baud_base = si_alp_clock(sih);
7371 baud_base = si_clock(sih);
7416 si_serial_baudrate_set(si_t *sih, void* serialconf)
7426 osh = si_osh(sih);
7428 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
7430 if (((sih->cccaps) & CC_CAP_UARTS_MASK) <= serialparam->interf) {
7439 baud_base = si_get_uart_clock(sih, osh, cc);
7516 si_serial_baudrate_get(si_t *sih, void* param, void* arg)
7527 osh = si_osh(sih);
7528 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
7530 if (((sih->cccaps) & CC_CAP_UARTS_MASK) <= serialarg->interf) {
7534 baud_base = si_get_uart_clock(sih, osh, cc);