Lines Matching refs:si_pmu_chipcontrol
659 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT),
688 pmu_chipcontrol = si_pmu_chipcontrol(sih, 1, 0, 0);
901 si_pmu_chipcontrol(sih, 1, ~0, pmu_chipcontrol);
1128 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, (1 << 31), (1 << 31));
1179 si_pmu_chipcontrol(sih, 2, ~0, pmu_chipcontrol2);
1180 reg = si_pmu_chipcontrol(sih, 2, 0, 0);
1418 si_pmu_chipcontrol(sih, PMU1_PLL0_CHIPCTL1, 0x0000000F, 0x0000000A);
2221 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
2226 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
2253 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE, CCTRL_4313_12MA_LED_DRIVE);
4123 pmu_var->pmu_chipcontrol1[i] = si_pmu_chipcontrol(sih, i, 0, 0);
4224 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x003c0000, j);
4241 reg_val = si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0, 0);
6943 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x01000000, 0x01000000);
6945 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x10, 0x10);
6948 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0xf0000, 0x10000);
6954 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x10, 0x10);
6957 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0x80, 0);
6960 si_pmu_chipcontrol(sih, CHIPCTRLREG1, 0xf0000, 0x10000);
6982 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x1c0000, 0x0);
6985 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x100000, 0x100000);
6989 si_pmu_chipcontrol(sih, CHIPCTRLREG2, 0x3c0000, 0x3c0000);
7216 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << USBAPP_CLK_BIT), 0);
7220 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << PCIE_CLK_BIT), 0);
7228 si_pmu_chipcontrol(sih, PMU_CHIPCTL3, PMU43602_CC3_ARMCR4_DBG_CLK,
7237 si_pmu_chipcontrol(sih, PMU_CHIPCTL5,
7243 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, (1 << ARMCR4_DBG_CLK_BIT), 0);
7276 si_pmu_chipcontrol(sih, PMU_CHIPCTL2,
7324 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, mask, val);
7332 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, PLL_DIV2_MASK, PLL_DIV2_DIS_OP);