Lines Matching refs:SI_CC_IDX
292 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
317 si_setcoreidx(&sii->pub, SI_CC_IDX);
664 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT,
669 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, jtagctrl),
689 chipcontrol = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
902 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
911 return si_corereg(sih, SI_CC_IDX, offset, mask, val);
918 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, regidx);
919 return si_corereg(sih, SI_CC_IDX, offset, mask, val);
926 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_input[reg]), 0, 0);
933 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_output[reg]), mask, val);
943 return (si_corereg(sih, SI_CC_IDX, offs, CI_ECI, (enable ? CI_ECI : 0)));
971 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
972 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpioctl),
986 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
990 si_corereg(sih, SI_CC_IDX, reg_offset, GCIMASK_4B(pos), GCIPOSVAL_4B(value, pos));
992 val_32 = si_corereg(sih, SI_CC_IDX, reg_offset, 0, 0);
1008 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, ring_idx);
1061 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_wakemask),
1082 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intmask),
1085 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intmask),
1290 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, 0);
1291 gpio_status[0] = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), 0, 0);
1292 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), ~0, ~0);
1294 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, 1);
1295 gpio_status[1] = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), 0, 0);
1296 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_gpiostatus), ~0, ~0);
1324 gci_intstatus = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_intstat), 0, 0);
1678 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, reg);
1679 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_chipctrl), mask, val);
1692 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_indirect_addr), ~0, reg);
1694 return si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_chipsts), 0, 0);
1781 cap1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gci_corecaps1), 0, 0);
1915 origidx = SI_CC_IDX;
1958 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 100);
2191 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
2219 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
2793 if (idx == SI_CC_IDX) {
3196 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), ~0, 0x2);
3220 pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks);
3230 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4096 reg_val = si_corereg(&sii->pub, SI_CC_IDX, offset, mask, val);
4138 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i);
4139 pmu_var->pmu_rsrc_up_down_timer[i] = si_corereg(sih, SI_CC_IDX,
4145 si_corereg(sih, SI_CC_IDX, RSRCTABLEADDR, ~0, i);
4146 pmu_var->rsrc_dep_mask[i] = si_corereg(sih, SI_CC_IDX, PMU_RES_DEP_MASK, 0, 0);
4766 si_corereg(&sii->pub, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), ~0, w);
4821 return (si_setcoreidx(sih, SI_CC_IDX));
4848 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4870 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4892 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4960 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
4977 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
4994 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
5005 return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
5015 return (si_corereg(sih, SI_CC_IDX,
5028 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
5048 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
5145 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
5751 si_corereg(sih, SI_CC_IDX,
5773 si_corereg(sih, SI_CC_IDX, offset, mask, val);
5777 si_corereg(sih, SI_CC_IDX,
5811 si_corereg(sih, SI_CC_IDX, offset, CLKCTL_STS_SECI_CLK_REQ, val);
6039 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFF); /* 4MBaud */
6046 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44);
6056 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFE);
6058 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44);
6062 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x22);
6067 si_corereg(sih, SI_CC_IDX, offset, 0xFF,
6070 si_corereg(sih, SI_CC_IDX, offset,
6075 si_corereg(sih, SI_CC_IDX, offset, ALLONES_32, ECI_MACCTRLLO_BITS);
6077 si_corereg(sih, SI_CC_IDX, offset, 0xFFFF, ECI_MACCTRLHI_BITS);
6438 cc = si_setcoreidx(sih, SI_CC_IDX);
6818 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
6843 data = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, fabid), 0, 0);
6861 cc = si_setcoreidx(sih, SI_CC_IDX);
6877 cc = si_setcoreidx(sih, SI_CC_IDX);
7013 pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0);
7015 return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0);
7233 uint32 tapsel = si_corereg(sih, SI_CC_IDX,
7428 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
7528 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);