Lines Matching refs:sii
39 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
40 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
42 static uint32 _sb_coresba(si_info_t *sii);
43 static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
45 #define SET_SBREG(sii, r, mask, val) \
46 W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
53 #define R_SBREG(sii, sbr) sb_read_sbreg((sii), (sbr))
54 #define W_SBREG(sii, sbr, v) sb_write_sbreg((sii), (sbr), (v))
55 #define AND_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
56 #define OR_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
59 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
71 if (PCMCIA(sii)) {
72 INTR_OFF(sii, intr_val);
74 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
78 val = R_REG(sii->osh, sbr);
80 if (PCMCIA(sii)) {
82 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
83 INTR_RESTORE(sii, intr_val);
90 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
103 if (PCMCIA(sii)) {
104 INTR_OFF(sii, intr_val);
106 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
110 if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
112 dummy = R_REG(sii->osh, sbr);
114 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
115 dummy = R_REG(sii->osh, sbr);
117 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
119 dummy = R_REG(sii->osh, sbr);
121 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
122 dummy = R_REG(sii->osh, sbr);
124 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
127 W_REG(sii->osh, sbr, v);
129 if (PCMCIA(sii)) {
131 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
132 INTR_RESTORE(sii, intr_val);
139 si_info_t *sii;
142 sii = SI_INFO(sih);
143 sb = REGS2SB(sii->curmap);
145 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
151 si_info_t *sii;
156 sii = SI_INFO(sih);
158 INTR_OFF(sii, intr_val);
163 intflag = R_SBREG(sii, &sb->sbflagst);
165 INTR_RESTORE(sii, intr_val);
173 si_info_t *sii;
176 sii = SI_INFO(sih);
177 sb = REGS2SB(sii->curmap);
179 return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
185 si_info_t *sii;
189 sii = SI_INFO(sih);
190 sb = REGS2SB(sii->curmap);
196 W_SBREG(sii, &sb->sbintvec, vec);
201 BCMATTACHFN(_sb_coreidx)(si_info_t *sii, uint32 sba)
205 for (i = 0; i < sii->numcores; i ++)
206 if (sba == sii->coresba[i])
213 BCMATTACHFN(_sb_coresba)(si_info_t *sii)
218 switch (BUSTYPE(sii->pub.bustype)) {
220 sbconfig_t *sb = REGS2SB(sii->curmap);
221 sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));
226 sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
231 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
233 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
235 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
243 sbaddr = (uint32)(uintptr)sii->curmap;
258 si_info_t *sii;
261 sii = SI_INFO(sih);
262 sb = REGS2SB(sii->curmap);
264 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
270 si_info_t *sii;
274 sii = SI_INFO(sih);
275 sb = REGS2SB(sii->curmap);
276 sbidh = R_SBREG(sii, &sb->sbidhigh);
285 si_info_t *sii;
289 sii = SI_INFO(sih);
290 sb = REGS2SB(sii->curmap);
295 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
297 W_SBREG(sii, &sb->sbtmstatelow, w);
304 si_info_t *sii;
308 sii = SI_INFO(sih);
309 sb = REGS2SB(sii->curmap);
315 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
317 W_SBREG(sii, &sb->sbtmstatelow, w);
323 return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
330 si_info_t *sii;
334 sii = SI_INFO(sih);
335 sb = REGS2SB(sii->curmap);
342 w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
344 W_SBREG(sii, &sb->sbtmstatehigh, w);
348 return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
354 si_info_t *sii;
357 sii = SI_INFO(sih);
358 sb = REGS2SB(sii->curmap);
360 return ((R_SBREG(sii, &sb->sbtmstatelow) &
382 si_info_t *sii;
384 sii = SI_INFO(sih);
393 if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
397 if (!sii->regs[coreidx]) {
398 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
400 ASSERT(GOODREGS(sii->regs[coreidx]));
402 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
403 } else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
406 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
410 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
411 } else if (sii->pub.buscoreidx == coreidx) {
416 if (SI_FAST(sii))
417 r = (uint32 *)((char *)sii->curmap +
420 r = (uint32 *)((char *)sii->curmap +
428 INTR_OFF(sii, intr_val);
431 origidx = si_coreidx(&sii->pub);
434 r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
441 w = (R_SBREG(sii, r) & ~mask) | val;
442 W_SBREG(sii, r, w);
444 w = (R_REG(sii->osh, r) & ~mask) | val;
445 W_REG(sii->osh, r, w);
451 w = R_SBREG(sii, r);
453 if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
458 w = R_REG(sii->osh, r);
464 sb_setcoreidx(&sii->pub, origidx);
466 INTR_RESTORE(sii, intr_val);
486 si_info_t *sii;
488 sii = SI_INFO(sih);
496 if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
500 if (!sii->regs[coreidx]) {
501 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
503 ASSERT(GOODREGS(sii->regs[coreidx]));
505 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
506 } else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
509 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
513 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
514 } else if (sii->pub.buscoreidx == coreidx) {
519 if (SI_FAST(sii))
520 r = (uint32 *)((char *)sii->curmap +
523 r = (uint32 *)((char *)sii->curmap +
545 BCMATTACHFN(_sb_scan)(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
560 for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
561 sii->coresba[next] = sbba + (i * SI_CORE_SIZE);
564 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (sii->coresba[next] == sba)) {
566 sii->regs[next] = regs;
570 sii->curmap = _sb_setcoreidx(sii, next);
571 sii->curidx = next;
573 sii->coreid[next] = sb_coreid(&sii->pub);
577 if (sii->coreid[next] == CC_CORE_ID) {
578 chipcregs_t *cc = (chipcregs_t *)sii->curmap;
579 uint32 ccrev = sb_corerev(&sii->pub);
584 numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>
588 uint chip = CHIPID(sii->pub.chip);
604 sii->pub.issim ? "QT" : ""));
607 else if (sii->coreid[next] == OCP_CORE_ID) {
608 sbconfig_t *sb = REGS2SB(sii->curmap);
609 uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
612 sii->numcores = next + 1;
617 if (_sb_coreidx(sii, nsbba) != BADIDX)
620 nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
621 nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
630 sii->numcores = i + ncc;
631 return sii->numcores;
638 si_info_t *sii;
642 sii = SI_INFO(sih);
643 sb = REGS2SB(sii->curmap);
645 sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
650 origsba = _sb_coresba(sii);
653 sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
664 si_info_t *sii;
666 sii = SI_INFO(sih);
668 if (coreidx >= sii->numcores)
675 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
677 sii->curmap = _sb_setcoreidx(sii, coreidx);
678 sii->curidx = coreidx;
680 return (sii->curmap);
687 _sb_setcoreidx(si_info_t *sii, uint coreidx)
689 uint32 sbaddr = sii->coresba[coreidx];
692 switch (BUSTYPE(sii->pub.bustype)) {
695 if (!sii->regs[coreidx]) {
696 sii->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
697 ASSERT(GOODREGS(sii->regs[coreidx]));
699 regs = sii->regs[coreidx];
704 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);
705 regs = sii->curmap;
710 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
712 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
714 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
715 regs = sii->curmap;
722 if (!sii->regs[coreidx]) {
723 sii->regs[coreidx] = (void *)(uintptr)sbaddr;
724 ASSERT(GOODREGS(sii->regs[coreidx]));
726 regs = sii->regs[coreidx];
741 sb_admatch(si_info_t *sii, uint asidx)
746 sb = REGS2SB(sii->curmap);
777 si_info_t *sii;
780 sii = SI_INFO(sih);
781 sb = REGS2SB(sii->curmap);
784 return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;
791 si_info_t *sii;
793 sii = SI_INFO(sih);
795 return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));
802 si_info_t *sii;
804 sii = SI_INFO(sih);
806 return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
812 sb_serr_clear(si_info_t *sii)
819 INTR_OFF(sii, intr_val);
820 origidx = si_coreidx(&sii->pub);
822 for (i = 0; i < sii->numcores; i++) {
823 corereg = sb_setcoreidx(&sii->pub, i);
826 if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) {
827 AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR);
829 sb_coreid(&sii->pub)));
834 sb_setcoreidx(&sii->pub, origidx);
835 INTR_RESTORE(sii, intr_val);
845 si_info_t *sii;
854 sii = SI_INFO(sih);
856 if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
860 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32));
863 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32), stcmd);
867 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32));
870 sb_serr_clear(sii);
871 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32), stcmd);
875 imstate = sb_corereg(sih, sii->pub.buscoreidx,
878 sb_corereg(sih, sii->pub.buscoreidx,
889 if (sii->pub.socirev == SONICS_2_2)
893 imerrlog = sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, 0, 0);
895 imerrloga = sb_corereg(sih, sii->pub.buscoreidx,
899 sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, ~0, 0);
907 } else if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
909 INTR_OFF(sii, intr_val);
916 imstate = R_SBREG(sii, &sb->sbimstate);
919 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
923 tmstate = R_SBREG(sii, &sb->sbtmstatehigh);
927 sb_serr_clear(sii);
929 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK);
930 AND_SBREG(sii, &sb->sbtmstatelow, ~SBTML_INT_ACK);
934 INTR_RESTORE(sii, intr_val);
953 si_info_t *sii;
957 sii = SI_INFO(sih);
959 origidx = sii->curidx;
962 INTR_OFF(sii, intr_val);
965 if (sii->pub.ccrev != NOREV) {
970 W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);
971 W_REG(sii->osh, &ccregs->broadcastdata, 0x0);
972 } else if (PCI(sii)) {
976 W_REG(sii->osh, &pciregs->bcastaddr, SB_COMMIT);
977 W_REG(sii->osh, &pciregs->bcastdata, 0x0);
983 INTR_RESTORE(sii, intr_val);
989 si_info_t *sii;
993 sii = SI_INFO(sih);
995 ASSERT(GOODREGS(sii->curmap));
996 sb = REGS2SB(sii->curmap);
999 if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
1003 if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
1007 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
1008 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1011 SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
1012 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
1015 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
1016 OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
1017 dummy = R_SBREG(sii, &sb->sbimstate);
1020 SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
1024 W_SBREG(sii, &sb->sbtmstatelow,
1027 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1032 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
1033 AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
1037 W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
1049 si_info_t *sii;
1053 sii = SI_INFO(sih);
1054 ASSERT(GOODREGS(sii->curmap));
1055 sb = REGS2SB(sii->curmap);
1067 W_SBREG(sii, &sb->sbtmstatelow,
1070 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1074 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {
1075 W_SBREG(sii, &sb->sbtmstatehigh, 0);
1077 if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
1078 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
1082 W_SBREG(sii, &sb->sbtmstatelow,
1084 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1089 W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
1090 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1122 si_info_t *sii;
1128 sii = SI_INFO(sih);
1135 switch (BUSTYPE(sii->pub.bustype)) {
1137 idx = sii->pub.buscoreidx;
1155 INTR_OFF(sii, intr_val);
1160 tmp = R_SBREG(sii, &sb->sbimconfiglow);
1162 W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
1166 INTR_RESTORE(sii, intr_val);
1223 si_info_t *sii;
1227 sii = SI_INFO(sih);
1228 origidx = sii->curidx;
1230 INTR_OFF(sii, intr_val);
1232 for (i = 0; i < sii->numcores; i++) {
1235 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
1237 if (sii->pub.socirev > SONICS_2_2)
1239 sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
1240 sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));
1244 R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),
1245 R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),
1246 R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));
1250 INTR_RESTORE(sii, intr_val);