Lines Matching refs:bcm_bprintf
1883 bcm_bprintf(b, "FORCEHT %d pcie_polarity 0x%x pcie_aspm_ovr 0x%x\n",
2116 bcm_bprintf(b, "PCIE link speed: %d\n", pcie_get_link_speed(pch));
2143 bcm_bprintf(b, "PLPRegs \t");
2147 bcm_bprintf(b, "%s", bitfield_dump_buf);
2149 bcm_bprintf(b, "\n");
2150 bcm_bprintf(b, "DLLPRegs \t");
2154 bcm_bprintf(b, "%s", bitfield_dump_buf);
2156 bcm_bprintf(b, "\n");
2157 bcm_bprintf(b, "TLPRegs \t");
2161 bcm_bprintf(b, "%s", bitfield_dump_buf);
2163 bcm_bprintf(b, "\n");
2168 bcm_bprintf(b, "SERDES regs \n");
2171 bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
2173 bcm_bprintf(b, "block IEEE0, offset 2: 0x%x\n", reg_val);
2175 bcm_bprintf(b, "block IEEE1, lanestatus: 0x%x\n", reg_val);
2177 bcm_bprintf(b, "block IEEE1, lanestatus2: 0x%x\n", reg_val);
2179 bcm_bprintf(b, "MDIO_DEV_BLK4, lanetest0: 0x%x\n", reg_val);
2181 bcm_bprintf(b, "MDIO_DEV_TXPLL, pllcontrol: 0x%x\n", reg_val);
2183 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer1: 0x%x\n", reg_val);
2185 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer2: 0x%x\n", reg_val);
2187 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer3: 0x%x\n", reg_val);
2189 bcm_bprintf(b, "MDIO_DEV_TXPLL, freqdetcounter: 0x%x\n", reg_val);
2192 bcm_bprintf(b, "rxtimer1 0x%x ", reg_val);
2194 bcm_bprintf(b, "rxCDR 0x%x ", reg_val);
2196 bcm_bprintf(b, "rxCDRBW 0x%x\n", reg_val);