Lines Matching refs:PCIE
46 uint8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
47 uint8 pciecap_devctrl_offset; /* PCIE DevControl reg offset in the config space */
57 uint8 pciecap_devctrl2_offset; /* PCIE DevControl2 reg offset in the config space */
58 uint32 pciecap_ltr0_reg_offset; /* PCIE LTR0 reg offset in the config space */
59 uint32 pciecap_ltr1_reg_offset; /* PCIE LTR1 reg offset in the config space */
60 uint32 pciecap_ltr2_reg_offset; /* PCIE LTR2 reg offset in the config space */
99 #define PCIE(sih) (PCIE_GEN1(sih) || PCIE_GEN2(sih))
768 ASSERT(PCIE(sih));
2107 /* Dump PCIE Info */
2116 bcm_bprintf(b, "PCIE link speed: %d\n", pcie_get_link_speed(pch));
2125 /** Dump PCIE PLP/DLLP/TLP diagnostic registers */