Lines Matching defs:nc
84 static int nandcore_poll(si_t *sih, nandregs_t *nc);
108 nandcore_cmd(osl_t *osh, nandregs_t *nc, uint opcode)
110 W_REG(osh, &nc->cmd_start, opcode);
151 nandregs_t *nc = (nandregs_t *)nfl->core;
176 err_hard_reg = R_REG(osh, &nc->uncorr_error_count);
177 err_soft_reg = R_REG(osh, &nc->read_error_count);
181 OR_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
184 AND_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
192 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
194 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
195 W_REG(osh, &nc->cmd_address, (uint32)offset + col);
198 nandcore_cmd(osh, nc, NANDCMD_PAGE_RD);
201 if ((ret = nandcore_poll(nfl->sih, nc)) < 0)
210 *to = R_REG(osh, &nc->flash_cache[i]);
220 reg = R_REG(osh, &nc->spare_area_read_ofs[i]);
226 reg = R_REG(osh, &nc->spare_area_read_ofs[i]);
236 if (err_hard_reg != R_REG(osh, &nc->uncorr_error_count)) {
237 int era = (R_REG(osh, &nc->intfc_status) & NANDIST_ERASED);
241 err_hard_reg = R_REG(osh, &nc->uncorr_error_count);
254 *serr = R_REG(osh, &nc->read_error_count) - err_soft_reg;
263 nandregs_t *nc = (nandregs_t *)nfl->core;
286 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
290 OR_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
293 AND_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
301 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
303 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
304 W_REG(osh, &nc->cmd_address, (uint32)offset + col);
312 W_REG(osh, &nc->flash_cache[i], *from);
324 W_REG(osh, &nc->spare_area_write_ofs[i], reg);
332 W_REG(osh, &nc->spare_area_write_ofs[i], reg);
338 W_REG(osh, &nc->spare_area_write_ofs[i],
347 W_REG(osh, &nc->spare_area_write_ofs[i],
355 nandcore_cmd(osh, nc, NANDCMD_PAGE_PROG);
357 ret = nandcore_poll(nfl->sih, nc);
364 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
418 nandregs_t *nc = nfl->core;
430 reg = R_REG(osh, &nc->config_cs0);
435 W_REG(osh, &nc->config_cs0, reg);
438 reg = R_REG(osh, &nc->acc_control_cs0);
444 W_REG(osh, &nc->acc_control_cs0, reg);
452 reg = R_REG(osh, &nc->acc_control_cs0);
458 W_REG(osh, &nc->acc_control_cs0, reg);
465 nandregs_t *nc = nfl->core;
482 reg = R_REG(osh, nfl->chipidx ? &nc->timing_2_cs1 : &nc->timing_2_cs0);
500 W_REG(osh, nfl->chipidx ? &nc->timing_1_cs1 : &nc->timing_1_cs0, reg);
511 W_REG(osh, nfl->chipidx ? &nc->timing_2_cs1 : &nc->timing_2_cs0, reg);
522 nandregs_t *nc;
537 if ((nc = (nandregs_t *)si_setcore(sih, NS_NAND_CORE_ID, 0)) == NULL)
540 if (R_REG(NULL, &nc->flash_device_id) == 0)
550 nandcore.core = (void *)nc;
571 nandcore_cmd(osh, nc, NANDCMD_FLASH_RESET);
572 if (nandcore_poll(sih, nc) < 0) {
576 nandcore_cmd(osh, nc, NANDCMD_ID_RD);
577 if (nandcore_poll(sih, nc) < 0) {
586 id = R_REG(osh, &nc->flash_device_id);
587 id2 = R_REG(osh, &nc->flash_device_id_ext);
605 ncf = R_REG(osh, &nc->config_cs0);
659 acc_control = R_REG(osh, &nc->acc_control_cs0);
722 W_REG(osh, &nc->acc_control_cs0, acc_control);
725 if (R_REG(osh, &nc->acc_control_cs0) & NANDAC_CS0_SECTOR_SIZE_1K) {
726 AND_REG(osh, &nc->acc_control_cs0, ~NANDAC_CS0_PARTIAL_PAGE_EN);
728 AND_REG(osh, &nc->acc_control_cs0, ~NANDAC_CS0_FAST_PGM_RDIN);
766 nandcore_poll(si_t *sih, nandregs_t *nc)
777 if ((R_REG(osh, &nc->intfc_status) & pollmask) == pollmask) {
826 nandregs_t *nc = (nandregs_t *)nfl->core;
842 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
845 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
846 W_REG(osh, &nc->cmd_ext_address, (reg | ((offset >> 32) & NANDCMD_EXT_ADDR_MASK)));
848 W_REG(osh, &nc->cmd_address, (uint32)offset);
849 nandcore_cmd(osh, nc, NANDCMD_BLOCK_ERASE);
850 if (nandcore_poll(sih, nc) < 0)
854 W_REG(osh, &nc->cmd_start, NANDCMD_STATUS_RD);
855 if (nandcore_poll(sih, nc) < 0)
858 status = R_REG(osh, &nc->intfc_status) & NANDIST_STATUS;
865 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
874 nandregs_t *nc = (nandregs_t *)nfl->core;
894 OR_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
906 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
908 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
909 W_REG(osh, &nc->cmd_address, (uint32)addr + col);
912 nandcore_cmd(osh, nc, NANDCMD_PAGE_RD);
915 if (nandcore_poll(sih, nc) < 0) {
930 oob_bi = R_REG(osh, &nc->spare_area_read_ofs[0]);
932 reg = R_REG(osh, &nc->spare_area_read_ofs[j]);
936 reg = R_REG(osh, &nc->spare_area_read_ofs[j]);
958 nandregs_t *nc = (nandregs_t *)nfl->core;
975 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
978 W_REG(osh, &nc->cmd_address, offset);
979 nandcore_cmd(osh, nc, NANDCMD_BLOCK_ERASE);
980 if (nandcore_poll(sih, nc) < 0) {
990 reg = R_REG(osh, &nc->acc_control_cs0);
994 W_REG(osh, &nc->acc_control_cs0, reg);
1002 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
1004 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
1006 W_REG(osh, &nc->cmd_address, (uint32)off);
1011 W_REG(osh, &nc->spare_area_write_ofs[0], 0);
1012 W_REG(osh, &nc->spare_area_write_ofs[1], 0);
1013 W_REG(osh, &nc->spare_area_write_ofs[2], 0);
1014 W_REG(osh, &nc->spare_area_write_ofs[3], 0);
1019 nandcore_cmd(osh, nc, NANDCMD_SPARE_PROG);
1020 if (nandcore_poll(sih, nc) < 0) {
1031 W_REG(osh, &nc->spare_area_write_ofs[0], 0xffffffff);
1032 W_REG(osh, &nc->spare_area_write_ofs[1], 0xffffffff);
1033 W_REG(osh, &nc->spare_area_write_ofs[2], 0xffffffff);
1034 W_REG(osh, &nc->spare_area_write_ofs[3], 0xffffffff);
1040 reg = R_REG(osh, &nc->acc_control_cs0);
1044 W_REG(osh, &nc->acc_control_cs0, reg);
1047 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
1061 nandregs_t *nc = (nandregs_t *)nfl->core;
1066 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
1067 W_REG(osh, &nc->cmd_ext_address, (reg | ((addr >> 32) & NANDCMD_EXT_ADDR_MASK)));
1068 W_REG(osh, &nc->cmd_address, (uint32)addr);
1087 nandregs_t *nc = (nandregs_t *)nfl->core;
1092 reg = R_REG(osh, &nc->cmd_ext_address);
1095 W_REG(osh, &nc->cmd_ext_address, reg);
1108 nandregs_t *nc = (nandregs_t *)nfl->core;
1119 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
1120 nandcore_cmd(osh, nc, NANDCMD_BLOCK_ERASE);
1123 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
1130 nandcore_cmd(osh, nc, NANDCMD_PAGE_RD);
1134 nandcore_cmd(osh, nc, NANDCMD_FLASH_RESET);
1138 nandcore_cmd(osh, nc, NANDCMD_ID_RD);
1143 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
1144 nandcore_cmd(osh, nc, NANDCMD_STATUS_RD);
1147 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
1168 nandregs_t *nc = (nandregs_t *)nfl->core;
1173 ret = nandcore_poll(nfl->sih, nc);
1175 *status = R_REG(osh, &nc->intfc_status) & NANDIST_STATUS;
1185 nandregs_t *nc = (nandregs_t *)nfl->core;
1197 OR_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0,
1205 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
1207 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
1208 W_REG(osh, &nc->cmd_address, (uint32)(addr + col));
1211 nandcore_cmd(osh, nc, NANDCMD_PAGE_RD);
1214 if (nandcore_poll(sih, nc))
1226 reg = R_REG(osh, &nc->spare_area_read_ofs[i]);
1232 reg = R_REG(osh, &nc->spare_area_read_ofs[i]);
1249 nandregs_t *nc = (nandregs_t *)nfl->core;
1262 AND_REG(osh, &nc->cs_nand_select, ~NANDCSEL_NAND_WP);
1268 reg = R_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0);
1274 W_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0, reg);
1281 reg = (R_REG(osh, &nc->cmd_ext_address) & ~NANDCMD_EXT_ADDR_MASK);
1283 W_REG(osh, &nc->cmd_ext_address, (reg | ext_addr));
1284 W_REG(osh, &nc->cmd_address, (uint32)(addr + col));
1291 W_REG(osh, &nc->flash_cache[i], 0xffffffff);
1301 W_REG(osh, &nc->spare_area_write_ofs[i], reg);
1308 W_REG(osh, &nc->spare_area_write_ofs[i], reg);
1314 W_REG(osh, &nc->spare_area_write_ofs[i], 0xffffffff);
1320 nandcore_cmd(osh, nc, NANDCMD_PAGE_PROG);
1322 if (nandcore_poll(sih, nc)) {
1333 reg = R_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0);
1339 W_REG(osh, nfl->chipidx ? &nc->acc_control_cs1 : &nc->acc_control_cs0, reg);
1342 OR_REG(osh, &nc->cs_nand_select, NANDCSEL_NAND_WP);
1365 nandregs_t *nc = (nandregs_t *)nfl->core;
1372 return R_REG(osh, id_ext ? &nc->flash_device_id_ext : &nc->flash_device_id);
1374 return (R_REG(osh, &nc->intfc_status) & NANDIST_STATUS);