Lines Matching refs:xtal
72 static void si_pmu0_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
73 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
74 static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
75 static void si_pmu2_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
85 bool si_pmu_update_pllcontrol(si_t *sih, osl_t *osh, uint32 xtal, bool update_required);
349 "Invalid/Unsupported xtal value %d";
3207 BCMATTACHFN(si_pmu0_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
3214 if (xt->freq == xtal)
3219 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
3303 /** query alp/xtal clock frequency */
3582 * PLL control register table giving info about the xtal supported for 4335.
3608 * PLL control register values(all registers) for the xtal supported for 4335.
3636 * PLL control register table giving info about the xtal supported for 4335.
3646 * PLL control register values(all registers) for the xtal supported for 4335.
3679 /* PLL control register table giving info about the xtal supported for 4345 series */
3706 * PLL control register table giving info about the xtal supported for 43242
3720 * PLL control register table giving info about the xtal supported for 4350
3730 * PLL control register table giving info about the xtal supported for 4335.
3745 /* PLL control register values(all registers) for the xtal supported for 43242.
3797 /** returns xtal table for each chip */
3847 /** returns chip specific PLL settings for default xtal frequency and VCO output frequency */
3974 /** query alp/xtal clock frequency */
4122 * 'xtal' : xtal frequency in [KHz]
4131 BCMATTACHFN(si_pmu_pllctrlreg_update)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal,
4146 /* Program the PLL control register if the xtal value matches with the table entry value */
4148 /* If the entry does not match the xtal and spur_mode just continue the loop */
4149 if (!((pllctrlreg_update[indx].clock == (uint16)xtal) &&
4170 BCMATTACHFN(si_pmu_set_4345_pllcontrol_regs)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4203 ASSERT(xtal <= 0xFFFFFFFF / 1000);
4222 /* xtal and FVCO are in kHz. xtal/p1div must be <= 50MHz */
4223 p1div = 1 + (uint8) ((xtal * 1000) / 50000000UL);
4224 ndiv_int = (fvco * p1div) / xtal;
4226 /* ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 24)) / xtal) */
4227 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 24, 0);
4228 bcm_uint64_divide(&ndiv_frac, temp_high, temp_low, xtal);
4239 /* HSIC DFLL freq_target N_divide_ratio = 4096 * FVCO / xtal */
4242 ((((uint32) fvco << 12) / xtal) & 0x000FFFFF);
4244 ndiv_int = (fvco * p1div) / xtal;
4247 * ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 20)) /
4248 * xtal)
4250 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 20, 0);
4251 bcm_uint64_divide(&ndiv_frac, temp_high, temp_low, xtal);
4260 PMU_MSG(("xtal PLLCTRL0 PLLCTRL1 PLLCTRL2 PLLCTRL3"));
4262 PMU_MSG(("%d ", xtal));
4295 BCMATTACHFN(si_pmu_update_pllcontrol)(si_t *sih, osl_t *osh, uint32 xtal, bool update_required)
4311 * PLL control register even if it is default xtal.
4317 xtal = xtalfreq;
4320 if (xtal) {
4321 /* CASE2: If the xtal value was calculated, program the PLL control
4322 * registers only if it is not default xtal value.
4324 if (xtal != (si_pmu_def_alp_clock(sih, osh)/1000))
4327 /* CASE3: If the xtal obtained is "0", ie., clock is not measured, then
4329 * pmucontrol register with the default xtal value.
4331 xtal = si_pmu_def_alp_clock(sih, osh)/1000;
4418 if (xtal == XTAL_DEFAULT_4350)
4453 * xtal. NOTE THAT, THIS IS not DONE FOR 43239,
4458 * the xf for the xtal being programmed but don't program the registers now
4461 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update,
4464 /* Program the PLL based on the xtal value. */
4469 tmp |= (((((xtal + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
4475 printf(rstr_Invalid_Unsupported_xtal_value_D, xtal);
4484 /* Update the PLL control register based on the xtal used. */
4486 si_pmu_pllctrlreg_update(sih, osh, cc, xtal, 0, pllctrlreg_update, array_size,
4500 xtal = 0;
4518 si_pmu_set_4345_pllcontrol_regs(sih, osh, cc, xtal);
4520 xtal = 0;
4526 /* Program the PLL based on the xtal value. */
4527 if (xtal != 0) {
4531 if (xt->fref == xtal)
4546 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
4987 BCMATTACHFN(si_pmu2_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4994 if (xtal == 0) {
4995 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
5000 if (xt->fref == xtal)
5005 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n",
5006 xtal / 1000, xtal % 1000));
5020 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
5107 /** Query ALP/xtal clock frequency */
5148 BCMATTACHFN(si_pmu1_pllinit1)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
5178 (si_pmu_update_pllcontrol(sih, osh, xtal, FALSE) == FALSE))
5185 si_pmu_update_pllcontrol(sih, osh, xtal, TRUE);
5204 * case the xtal frequency is unknown to the s/w so we need to call
5208 BCMATTACHFN(si_pmu1_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
5217 if (xtal == 0) {
5218 PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
5224 if (xt->fref == xtal)
5231 PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n",
5232 xtal / 1000, xtal % 1000));
5247 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
8317 /* HSIC sprom_present_strap=1:40 mHz xtal */
8497 * HW4350-275: Chip wedge due to xtal startup issue when WL is in SR
8503 * which selects xtal core size between