Lines Matching refs:sih
72 static void si_pmu0_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
73 static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
74 static void si_pmu1_pllinit1(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
75 static void si_pmu2_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal);
76 static void si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
78 static void si_pmu_pll_off_isdone(si_t *sih, osl_t *osh, chipcregs_t *cc);
79 static void si_pmu_pll_on(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 min_mask,
81 void si_pmu_otp_pllcontrol(si_t *sih, osl_t *osh);
82 void si_pmu_otp_regcontrol(si_t *sih, osl_t *osh);
83 void si_pmu_otp_chipcontrol(si_t *sih, osl_t *osh);
84 uint32 si_pmu_def_alp_clock(si_t *sih, osl_t *osh);
85 bool si_pmu_update_pllcontrol(si_t *sih, osl_t *osh, uint32 xtal, bool update_required);
86 static uint32 si_pmu_htclk_mask(si_t *sih);
88 static uint32 si_pmu0_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
89 static uint32 si_pmu0_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
90 static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
91 static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
92 static uint32 si_pmu2_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
93 static uint32 si_pmu2_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
96 static bool si_pmu_res_depfltr_bb(si_t *sih);
97 static bool si_pmu_res_depfltr_ncb(si_t *sih);
98 static bool si_pmu_res_depfltr_paldo(si_t *sih);
99 static bool si_pmu_res_depfltr_npaldo(si_t *sih);
100 static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, bool all);
101 static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 rsrc);
102 static void si_pmu_res_masks(si_t *sih, uint32 *pmin, uint32 *pmax);
103 static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid);
105 void si_pmu_set_4330_plldivs(si_t *sih, uint8 dacrate);
106 static int8 si_pmu_cbuckout_to_vreg_ctrl(si_t *sih, uint16 cbuck_mv);
108 int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, chipcregs_t *cc);
109 uint32 si_pmu_get_pmutime_diff(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *prev);
110 bool si_pmu_wait_for_res_pending(si_t *sih, osl_t *osh, chipcregs_t *cc, uint usec,
112 uint32 si_pmu_get_pmutimer(si_t *sih, osl_t *osh, chipcregs_t *cc);
137 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
139 pmu_corereg(sih, SI_CC_IDX, chipcontrol_addr, ~0, reg);
140 return pmu_corereg(sih, SI_CC_IDX, chipcontrol_data, mask, val);
145 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
147 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, ~0, reg);
148 return pmu_corereg(sih, SI_CC_IDX, regcontrol_data, mask, val);
153 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
155 pmu_corereg(sih, SI_CC_IDX, pllcontrol_addr, ~0, reg);
156 return pmu_corereg(sih, SI_CC_IDX, pllcontrol_data, mask, val);
171 si_pmu_pllupd(si_t *sih)
173 pmu_corereg(sih, SI_CC_IDX, pmucontrol,
221 static rsc_per_chip_t* si_pmu_get_rsc_positions(si_t *sih)
225 switch (CHIPID(sih->chip)) {
316 si_pmu_pllreset(si_t *sih)
323 if (!si_pmu_htclk_mask(sih))
326 osh = si_osh(sih);
328 origidx = si_coreidx(sih);
329 cc = si_setcoreidx(sih, SI_CC_IDX);
332 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
334 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_PLL_PLLCTL_UPD);
335 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
338 si_setcoreidx(sih, origidx);
364 BCMATTACHFN(si_pmu_otp_pllcontrol)(si_t *sih, osl_t *osh)
373 if (sih->pmurev >= 5) {
374 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT;
377 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT;
386 W_REG(osh, PMUREG(sih, pllcontrol_addr), i);
387 W_REG(osh, PMUREG(sih, pllcontrol_data), val);
396 BCMATTACHFN(si_pmu_otp_regcontrol)(si_t *sih, osl_t *osh)
404 if (sih->pmurev >= 5) {
405 vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT;
408 vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT;
417 W_REG(osh, PMUREG(sih, regcontrol_addr), i);
418 W_REG(osh, PMUREG(sih, regcontrol_data), val);
427 BCMATTACHFN(si_pmu_otp_chipcontrol)(si_t *sih, osl_t *osh)
433 if (sih->pmurev >= 5) {
434 cc_ctrlcnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT;
437 cc_ctrlcnt = (sih->pmucaps & PCAP_CC_MASK) >> PCAP_CC_SHIFT;
446 W_REG(osh, PMUREG(sih, chipcontrol_addr), i);
447 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
453 BCMATTACHFN(si_pmu_set_switcher_voltage)(si_t *sih, osl_t *osh,
456 ASSERT(sih->cccaps & CC_CAP_PMU);
458 W_REG(osh, PMUREG(sih, regcontrol_addr), 0x01);
459 W_REG(osh, PMUREG(sih, regcontrol_data), (uint32)(bb_voltage & 0x1f) << 22);
461 W_REG(osh, PMUREG(sih, regcontrol_addr), 0x00);
462 W_REG(osh, PMUREG(sih, regcontrol_data), (uint32)(rf_voltage & 0x1f) << 14);
471 BCMATTACHFN(si_pmu_set_ldo_voltage)(si_t *sih, osl_t *osh, uint8 ldo, uint8 voltage)
477 ASSERT(sih->cccaps & CC_CAP_PMU);
479 switch (CHIPID(sih->chip)) {
538 if (((sih->chipst & CST4325_PMUTOP_2B_MASK) >>
547 if (((sih->chipst & CST4325_PMUTOP_2B_MASK) >>
718 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, /* PMU VREG register */
720 pmu_corereg(sih, SI_CC_IDX, regcontrol_data,
723 si_pmu_regcontrol(sih, addr2, mask2 >> rshift2, (voltage & mask2) >> rshift2);
728 si_pmu_paref_ldo_enable(si_t *sih, osl_t *osh, bool enable)
732 ASSERT(sih->cccaps & CC_CAP_PMU);
734 switch (CHIPID(sih->chip)) {
748 pmu_corereg(sih, SI_CC_IDX, min_res_mask,
761 BCMINITFN(si_pmu_fast_pwrup_delay)(si_t *sih, osl_t *osh)
769 ASSERT(sih->cccaps & CC_CAP_PMU);
772 origidx = si_coreidx(sih);
773 cc = si_setcoreidx(sih, SI_CC_IDX);
776 if (ISSIM_ENAB(sih)) {
779 switch (CHIPID(sih->chip)) {
806 if (CHIPREV(sih->chiprev) < 4) {
841 rsc = si_pmu_get_rsc_positions(sih);
843 ilp = si_ilp_clock(sih);
844 pmudelay = (si_pmu_res_uptime(sih, osh, cc, rsc->ht_avail) +
849 rsc = si_pmu_get_rsc_positions(sih);
850 ilp = si_ilp_clock(sih);
851 pmudelay = (si_pmu_res_uptime(sih, osh, cc, rsc->ht_avail) +
860 } /* if (ISSIM_ENAB(sih)) */
863 si_setcoreidx(sih, origidx);
869 BCMATTACHFN(si_pmu_force_ilp)(si_t *sih, osl_t *osh, bool force)
873 ASSERT(sih->cccaps & CC_CAP_PMU);
875 oldpmucontrol = R_REG(osh, PMUREG(sih, pmucontrol));
877 W_REG(osh, PMUREG(sih, pmucontrol), oldpmucontrol &
880 W_REG(osh, PMUREG(sih, pmucontrol), oldpmucontrol |
904 bool (*filter)(si_t *sih); /* action is taken when filter is NULL or return TRUE */
2190 BCMATTACHFN(si_pmu_res_depfltr_bb)(si_t *sih)
2192 return (sih->boardflags & BFL_BUCKBOOST) != 0;
2197 BCMATTACHFN(si_pmu_res_depfltr_ncb)(si_t *sih)
2199 if (CHIPID(sih->chip) == BCM4325_CHIP_ID)
2200 return (CHIPREV(sih->chiprev) >= 2) && ((sih->boardflags & BFL_NOCBUCK) != 0);
2201 return ((sih->boardflags & BFL_NOCBUCK) != 0);
2206 BCMATTACHFN(si_pmu_res_depfltr_paldo)(si_t *sih)
2208 return (sih->boardflags & BFL_PALDO) != 0;
2213 BCMATTACHFN(si_pmu_res_depfltr_npaldo)(si_t *sih)
2215 return (sih->boardflags & BFL_PALDO) == 0;
2218 #define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \
2219 sih->boardtype == BCM94325BGABU_BOARD)
2226 si_pmu_res_masks(si_t *sih, uint32 *pmin, uint32 *pmax)
2230 si_info_t * sii = SI_INFO(sih);
2233 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
2236 switch (CHIPID(sih->chip)) {
2250 ASSERT(CHIPREV(sih->chiprev) >= 2);
2252 if (!(sih->boardflags & BFL_NOCBUCK))
2254 if (((sih->chipst & CST4325_PMUTOP_2B_MASK) >>
2257 if (!si_is_otp_disabled(sih))
2260 if ((sih->boardflags & BFL_BUCKBOOST) && (BCM94325_BBVDDIOSD_BOARDS(sih)))
2277 if (CHIPREV(sih->chiprev) < 2) {
2282 if (BUSTYPE(sih->bustype) == SI_BUS) {
2304 if (CHIPREV(sih->chiprev) >= 0x4) {
2310 if (CHIPREV(sih->chiprev) >= 0x3) {
2311 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1;
2336 if (SR_ENAB() && sr_isenab(sih)) {
2354 if (CHIPREV(sih->chiprev) >= 0x2) {
2360 if (!si_is_otp_disabled(sih))
2368 if (!(sih->boardflags & BFL_NOCBUCK))
2427 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2433 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2439 si_pmu_chipcontrol(sih, 3, 0x1, 0x1);
2465 if (SR_ENAB() && sr_isenab(sih))
2483 if (CST4350_IFC_MODE(sih->chipst) == CST4350_IFC_MODE_PCIE) {
2484 int L1substate = si_pcie_get_L1substate(sih);
2495 min_mask = pmu_corereg(sih, SI_CC_IDX,
2503 if (SR_ENAB() && sr_isenab(sih)) {
2506 if (CST4350_CHIPMODE_PCIE(sih->chipst) &&
2507 (CHIPREV(sih->chiprev) <= 5)) {
2522 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);
2530 if ((sih->chippkg == BCM4314SDIO_PKG_ID) ||
2531 (sih->chippkg == BCM4314SDIO_ARM_PKG_ID) ||
2532 (sih->chippkg == BCM4314SDIO_FPBGA_PKG_ID)) {
2621 BCMATTACHFN(si_pmu_resdeptbl_upd)(si_t *sih, osl_t *osh,
2631 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
2635 !(restable[tablesz].filter)(sih))
2641 W_REG(osh, PMUREG(sih, res_table_sel), i);
2646 W_REG(osh, PMUREG(sih, res_dep_mask),
2652 OR_REG(osh, PMUREG(sih, res_dep_mask),
2658 AND_REG(osh, PMUREG(sih, res_dep_mask),
2672 BCMATTACHFN(si_pmu_res_init)(si_t *sih, osl_t *osh)
2689 si_info_t* sii = SI_INFO(sih);
2691 ASSERT(sih->cccaps & CC_CAP_PMU);
2694 origidx = si_coreidx(sih);
2695 cc = si_setcoreidx(sih, SI_CC_IDX);
2713 switch (CHIPID(sih->chip)) {
2722 if (ISSIM_ENAB(sih)) {
2735 if (ISSIM_ENAB(sih)) {
2749 if (ISSIM_ENAB(sih)) {
2763 if (ISSIM_ENAB(sih)) {
2779 if (ISSIM_ENAB(sih)) {
2794 if (ISSIM_ENAB(sih)) {
2808 if (!((sih->chippkg == BCM4314PCIE_ARM_PKG_ID) ||
2809 (sih->chippkg == BCM4314PCIE_PKG_ID) ||
2810 (sih->chippkg == BCM4314DEV_PKG_ID)))
2813 W_REG(osh, PMUREG(sih, chipcontrol_addr), PMU_CHIPCTL3);
2814 tmp = R_REG(osh, PMUREG(sih, chipcontrol_data));
2816 W_REG(osh, PMUREG(sih, chipcontrol_data), tmp);
2821 if (ISSIM_ENAB(sih)) {
2830 if (CST4334_CHIPMODE_HSIC(sih->chipst)) {
2841 if (ISSIM_ENAB(sih)) {
2857 if (ISSIM_ENAB(sih)) {
2860 } else if ((CHIPID(sih->chip) == BCM4324_CHIP_ID) && (CHIPREV(sih->chiprev) <= 1)) {
2893 if (!CST4350_CHIPMODE_PCIE(sih->chipst)) {
2904 if (CHIPREV(sih->chiprev) < 4) {
2932 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
2940 W_REG(osh, PMUREG(sih, res_table_sel),
2942 W_REG(osh, PMUREG(sih, res_updn_timer),
2953 if (sih->pmurev >= 13) {
2961 W_REG(osh, PMUREG(sih, res_table_sel), (uint32)i);
2962 W_REG(osh, PMUREG(sih, res_updn_timer), r_val);
2966 si_pmu_resdeptbl_upd(sih, osh, pmu_res_depend_table, pmu_res_depend_table_sz);
2974 W_REG(osh, PMUREG(sih, res_table_sel), (uint32)i);
2975 W_REG(osh, PMUREG(sih, res_dep_mask), (uint32)bcm_strtoul(val, NULL, 0));
2982 if (BUSTYPE(sih->bustype) == PCI_BUS || BUSTYPE(sih->bustype) == SI_BUS) {
2985 if ((CHIPID(sih->chip) == BCM4345_CHIP_ID) && CST4345_CHIPMODE_PCIE(sih->chipst))
2987 else if (BCM4350_CHIP(sih->chip) && CST4350_CHIPMODE_PCIE(sih->chipst))
2989 else if (CHIPID(sih->chip) == BCM43602_CHIP_ID)
2993 si_pmu_resdeptbl_upd(sih, osh,
2999 si_pmu_res_masks(sih, &min_mask, &max_mask);
3002 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, FALSE);
3006 if (CHIPID(sih->chip) == BCM4319_CHIP_ID) {
3007 min_mask |= R_REG(osh, PMUREG(sih, min_res_mask));
3008 max_mask |= R_REG(osh, PMUREG(sih, max_res_mask));
3027 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) &&
3028 (CHIPREV(sih->chiprev) < 4) &&
3029 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) {
3031 W_REG(osh, PMUREG(sih, pllcontrol_addr), 6);
3032 W_REG(osh, PMUREG(sih, pllcontrol_data), 0x09048562);
3034 W_REG(osh, PMUREG(sih, pllcontrol_addr), 14);
3035 W_REG(osh, PMUREG(sih, pllcontrol_data), 0x09048562);
3036 si_pmu_pllupd(sih);
3037 } else if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
3038 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) &&
3039 (CHIPREV(sih->chiprev) >= 4) &&
3040 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) {
3044 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
3045 OR_REG(osh, PMUREG(sih, chipcontrol_data), 0x800);
3048 W_REG(osh, PMUREG(sih, pllcontrol_addr), 6);
3049 W_REG(osh, PMUREG(sih, pllcontrol_data), 0x080004e2);
3051 W_REG(osh, PMUREG(sih, pllcontrol_addr), 7);
3052 W_REG(osh, PMUREG(sih, pllcontrol_data), 0xE);
3054 W_REG(osh, PMUREG(sih, pllcontrol_addr), 14);
3055 W_REG(osh, PMUREG(sih, pllcontrol_data), 0x080004e2);
3057 W_REG(osh, PMUREG(sih, pllcontrol_addr), 15);
3058 W_REG(osh, PMUREG(sih, pllcontrol_data), 0xE);
3060 si_pmu_pllupd(sih);
3061 } else if ((CHIPID(sih->chip) == BCM43602_CHIP_ID ||
3062 CHIPID(sih->chip) == BCM43462_CHIP_ID) &&
3063 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) {
3078 OR_REG(osh, PMUREG(sih, max_res_mask), max_mask);
3087 OR_REG(osh, PMUREG(sih, max_res_mask), min_mask);
3093 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
3099 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);
3103 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) &&
3104 (BUSTYPE(sih->bustype) == PCI_BUS) &&
3105 (CHIPREV(sih->chiprev) < 4)) {
3108 pcie_clk_ctl_st = si_corereg(sih, 3, 0x1e0, 0, 0);
3109 si_corereg(sih, 3, 0x1e0, ~0, (pcie_clk_ctl_st | CCS_HTAREQ));
3112 si_pmu_wait_for_steady_state(sih, osh, cc);
3117 si_setcoreidx(sih, origidx);
3159 BCMATTACHFN(si_pmu0_sbclk4328)(si_t *sih, int freq)
3162 osl_t *osh = si_osh(sih);
3166 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU0_PLL0_PLLCTL0);
3167 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
3170 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
3174 oldmin = R_REG(osh, PMUREG(sih, min_res_mask));
3175 oldmax = R_REG(osh, PMUREG(sih, max_res_mask));
3176 W_REG(osh, PMUREG(sih, min_res_mask), oldmin & ~PMURES_BIT(RES4328_BB_PLL_PU));
3177 W_REG(osh, PMUREG(sih, max_res_mask), oldmax & ~PMURES_BIT(RES4328_BB_PLL_PU));
3186 SPINWAIT((R_REG(osh, PMUREG(sih, res_state)) & PMURES_BIT(RES4328_BB_PLL_PU)), PLL_DELAY*3);
3187 if (R_REG(osh, PMUREG(sih, res_state)) & PMURES_BIT(RES4328_BB_PLL_PU)) {
3194 ASSERT(!(R_REG(osh, PMUREG(sih, res_state)) & PMURES_BIT(RES4328_BB_PLL_PU)));
3198 W_REG(osh, PMUREG(sih, max_res_mask), oldmax);
3207 BCMATTACHFN(si_pmu0_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
3222 tmp = (R_REG(osh, PMUREG(sih, pmucontrol)) & PCTL_XTALFREQ_MASK) >>
3228 if (CHIPID(sih->chip) == BCM4328_CHIP_ID)
3229 si_pmu0_sbclk4328(sih, PMU0_PLL0_PC0_DIV_ARM_88MHZ);
3244 switch (CHIPID(sih->chip)) {
3246 AND_REG(osh, PMUREG(sih, min_res_mask), ~PMURES_BIT(RES4328_BB_PLL_PU));
3247 AND_REG(osh, PMUREG(sih, max_res_mask), ~PMURES_BIT(RES4328_BB_PLL_PU));
3250 AND_REG(osh, PMUREG(sih, min_res_mask), ~PMURES_BIT(RES5354_BB_PLL_PU));
3251 AND_REG(osh, PMUREG(sih, max_res_mask), ~PMURES_BIT(RES5354_BB_PLL_PU));
3262 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU0_PLL0_PLLCTL0);
3263 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
3268 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
3271 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU0_PLL0_PLLCTL1);
3272 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
3282 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
3285 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU0_PLL0_PLLCTL2);
3286 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
3290 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
3295 tmp = R_REG(osh, PMUREG(sih, pmucontrol));
3300 W_REG(osh, PMUREG(sih, pmucontrol), tmp);
3305 BCMINITFN(si_pmu0_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
3311 xf = (R_REG(osh, PMUREG(sih, pmucontrol)) & PCTL_XTALFREQ_MASK) >>
3324 BCMINITFN(si_pmu0_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
3330 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU0_PLL0_PLLCTL0);
3331 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
3799 BCMINITFN(si_pmu1_xtaltab0)(si_t *sih)
3801 switch (CHIPID(sih->chip)) {
3835 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
3840 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
3849 BCMINITFN(si_pmu1_xtaldef0)(si_t *sih)
3852 switch (CHIPID(sih->chip)) {
3901 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
3906 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
3915 BCMINITFN(si_pmu1_pllfvco0)(si_t *sih)
3918 switch (CHIPID(sih->chip)) {
3958 osh = si_osh(sih);
3959 return (si_pmu_cal_fvco(sih, osh));
3962 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
3967 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
3976 BCMINITFN(si_pmu1_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
3982 xf = (R_REG(osh, PMUREG(sih, pmucontrol)) & PCTL_XTALFREQ_MASK) >>
3984 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++)
3989 xt = si_pmu1_xtaldef0(sih);
4001 si_pmu_htclk_mask(si_t *sih)
4004 rsc_per_chip_t *rsc = si_pmu_get_rsc_positions(sih);
4008 switch (CHIPID(sih->chip))
4044 si_pmu_minresmask_htavail_set(si_t *sih, osl_t *osh, bool set_clear)
4047 switch (CHIPID(sih->chip)) {
4049 if ((R_REG(osh, PMUREG(sih, min_res_mask))) &
4051 AND_REG(osh, PMUREG(sih, min_res_mask),
4061 si_pll_minresmask_reset(si_t *sih, osl_t *osh)
4065 switch (CHIPID(sih->chip)) {
4068 AND_REG(osh, PMUREG(sih, min_res_mask),
4072 AND_REG(osh, PMUREG(sih, max_res_mask),
4076 OR_REG(osh, PMUREG(sih, max_res_mask),
4088 BCMATTACHFN(si_pmu_def_alp_clock)(si_t *sih, osl_t *osh)
4092 switch (CHIPID(sih->chip)) {
4131 BCMATTACHFN(si_pmu_pllctrlreg_update)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal,
4140 if (sih->pmurev >= 5) {
4141 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT;
4143 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT;
4158 W_REG(osh, PMUREG(sih, pllcontrol_addr), reg_offset);
4159 W_REG(osh, PMUREG(sih, pllcontrol_data),
4170 BCMATTACHFN(si_pmu_set_4345_pllcontrol_regs)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4193 uint32 fvco = si_pmu1_pllfvco0(sih); /* in [khz] */
4206 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
4210 si_pmu_pllcontrol(sih, 1, PMU1_PLL0_PC1_M4DIV_MASK,
4214 si_pmu_regcontrol(sih, 6, VREG6_4350_SR_EXT_CLKEN_MASK,
4218 si_pmu_regcontrol(sih, 6, VREG6_4350_SR_EXT_CLKEN_MASK,
4265 W_REG(osh, PMUREG(sih, pllcontrol_addr), i);
4266 W_REG(osh, PMUREG(sih, pllcontrol_data), PLL_control[i]);
4271 si_pmu_pllupd(sih);
4274 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (0<<6));
4275 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (1<<6));
4276 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (0<<6));
4279 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
4295 BCMATTACHFN(si_pmu_update_pllcontrol)(si_t *sih, osl_t *osh, uint32 xtal, bool update_required)
4324 if (xtal != (si_pmu_def_alp_clock(sih, osh)/1000))
4331 xtal = si_pmu_def_alp_clock(sih, osh)/1000;
4335 switch (CHIPID(sih->chip)) {
4350 if (sih->chippkg == BCM4335_WLBGA_PKG_ID) {
4353 if (CHIPREV(sih->chiprev) <= 1) {
4356 } else if (CHIPREV(sih->chiprev) == 2) {
4396 if (CHIPID(sih->chip) == BCM4354_CHIP_ID ||
4397 CHIPID(sih->chip) == BCM4356_CHIP_ID ||
4398 CHIPID(sih->chip) == BCM43569_CHIP_ID ||
4399 CHIPID(sih->chip) == BCM43570_CHIP_ID)
4402 if (CHIPREV(sih->chiprev) >= 3)
4427 if (CHIPREV(sih->chiprev) == 0) {
4448 origidx = si_coreidx(sih);
4449 cc = si_setcoreidx(sih, SI_CC_IDX);
4461 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update,
4467 tmp = R_REG(osh, PMUREG(sih, pmucontrol)) &
4472 W_REG(osh, PMUREG(sih, pmucontrol), tmp);
4486 si_pmu_pllctrlreg_update(sih, osh, cc, xtal, 0, pllctrlreg_update, array_size,
4491 switch (CHIPID(sih->chip)) {
4495 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2,
4505 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, PMU1_PLL0_PC1_M2DIV_MASK,
4513 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, PMU1_PLL0_PC1_M2DIV_MASK,
4518 si_pmu_set_4345_pllcontrol_regs(sih, osh, cc, xtal);
4530 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++)
4542 if (((R_REG(osh, PMUREG(sih, pmucontrol)) &
4552 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL0,
4560 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2,
4566 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL3, PMU1_PLL0_PC3_NDIV_FRAC_MASK, tmp);
4573 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL5, PMU1_PLL0_PC5_CLK_DRV_MASK, tmp);
4577 tmp = R_REG(osh, PMUREG(sih, pmucontrol)) &
4582 W_REG(osh, PMUREG(sih, pmucontrol), tmp);
4587 si_setcoreidx(sih, origidx);
4593 si_pmu_get_pmutimer(si_t *sih, osl_t *osh, chipcregs_t *cc)
4596 start = R_REG(osh, PMUREG(sih, pmutimer));
4597 if (start != R_REG(osh, PMUREG(sih, pmutimer)))
4598 start = R_REG(osh, PMUREG(sih, pmutimer));
4608 si_pmu_get_pmutime_diff(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *prev)
4614 pmutime_val = si_pmu_get_pmutimer(sih, osh, cc);
4632 si_pmu_wait_for_res_pending(si_t *sih, osl_t *osh, chipcregs_t *cc, uint usec,
4641 pmutime_prev = si_pmu_get_pmutimer(sih, osh, cc);
4643 res_pend = R_REG(osh, PMUREG(sih, res_pending));
4662 pmutime_elapsed += si_pmu_get_pmutime_diff(sih, osh, cc, &pmutime_prev);
4682 int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, chipcregs_t *cc)
4690 timedout = si_pmu_wait_for_res_pending(sih, osh, cc,
4705 timedout = si_pmu_wait_for_res_pending(sih, osh, cc,
4731 si_pmu_pll_off(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 *min_mask,
4737 *min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
4738 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4741 ht_req = si_pmu_htclk_mask(sih);
4745 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
4746 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
4747 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
4748 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
4749 BCM4350_CHIP(sih->chip) ||
4755 si_pmu_wait_for_steady_state(sih, osh, cc);
4757 OR_REG(osh, PMUREG(sih, max_res_mask), ht_req);
4764 AND_REG(osh, PMUREG(sih, min_res_mask), ~ht_req);
4765 AND_REG(osh, PMUREG(sih, max_res_mask), ~ht_req);
4776 si_pmu_pll_off_PARR(si_t *sih, osl_t *osh, uint32 *min_mask,
4784 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
4788 *min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
4789 *max_mask = R_REG(osh, PMUREG(sih, max_res_mask));
4791 ht_req = si_pmu_htclk_mask(sih);
4795 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
4796 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
4797 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
4798 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
4799 BCM4350_CHIP(sih->chip) ||
4805 si_pmu_wait_for_steady_state(sih, osh, cc);
4807 OR_REG(osh, PMUREG(sih, max_res_mask), ht_req);
4814 AND_REG(osh, PMUREG(sih, min_res_mask), ~ht_req);
4815 AND_REG(osh, PMUREG(sih, max_res_mask), ~ht_req);
4818 si_restore_core(sih, origidx, intr_val);
4823 si_pmu_pll_off_isdone(si_t *sih, osl_t *osh, chipcregs_t *cc)
4826 ht_req = si_pmu_htclk_mask(sih);
4827 SPINWAIT(((R_REG(osh, PMUREG(sih, res_state)) & ht_req) != 0),
4839 si_pmu_pll_on(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 min_mask_mask,
4844 ht_req = si_pmu_htclk_mask(sih);
4852 OR_REG(osh, PMUREG(sih, max_res_mask), max_mask_mask);
4855 OR_REG(osh, PMUREG(sih, min_res_mask), min_mask_mask);
4875 BCMINITFN(si_pmu2_xtaldef0)(si_t *sih)
4877 switch (CHIPID(sih->chip)) {
4884 if (ISSIM_ENAB(sih))
4894 if (ISSIM_ENAB(sih))
4908 BCMINITFN(si_pmu2_xtaltab0)(si_t *sih)
4910 switch (CHIPID(sih->chip)) {
4919 if (ISSIM_ENAB(sih))
4934 BCMATTACHFN(si_pmu2_pll_vars_init)(si_t *sih, osl_t *osh, chipcregs_t *cc)
4942 if (sih->pmurev >= 5) {
4943 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT;
4946 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT;
4967 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
4970 si_pmu_otp_pllcontrol(sih, osh);
4973 if (sih->pmurev >= 2)
4974 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_PLL_PLLCTL_UPD);
4979 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
4987 BCMATTACHFN(si_pmu2_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
4999 for (xt = si_pmu2_xtaltab0(sih), xt_idx = 0; xt != NULL && xt->fref != 0; xt++, xt_idx++) {
5010 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU15_PLL_PLLCTL0);
5011 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5024 switch (CHIPID(sih->chip)) {
5030 rsc = si_pmu_get_rsc_positions(sih);
5031 AND_REG(osh, PMUREG(sih, min_res_mask),
5033 AND_REG(osh, PMUREG(sih, max_res_mask),
5039 PMU_ERROR(("%s: Turn HT off for 0x%x????\n", __FUNCTION__, CHIPID(sih->chip)));
5044 W_REG(osh, PMUREG(sih, pllcontrol_data), pll0);
5046 if (CST4334_CHIPMODE_HSIC(sih->chipst)) {
5057 si_pmu_pllcontrol(sih, PMU15_PLL_PLLCTL5, PMU15_PLL_PC5_FREQTGT_MASK, hsic_freq);
5061 if (sih->pmurev >= 2)
5062 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_PLL_PLLCTL_UPD);
5066 si_pmu2_pll_vars_init(sih, osh, cc);
5071 BCMINITFN(si_pmu2_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
5076 switch (CHIPID(sih->chip)) {
5082 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU15_PLL_PLLCTL0);
5083 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5109 BCMINITFN(si_pmu2_alpclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
5114 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU15_PLL_PLLCTL0);
5115 pll0 = R_REG(osh, PMUREG(sih, pllcontrol_data));
5136 xt = si_pmu2_xtaldef0(sih);
5148 BCMATTACHFN(si_pmu1_pllinit1)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
5156 if (sih->pmurev >= 5) {
5157 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT;
5160 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT;
5178 (si_pmu_update_pllcontrol(sih, osh, xtal, FALSE) == FALSE))
5182 si_pmu_pll_off(sih, osh, cc, &min_mask, &max_mask, &clk_ctl_st);
5185 si_pmu_update_pllcontrol(sih, osh, xtal, TRUE);
5188 si_pmu_otp_pllcontrol(sih, osh);
5191 if (sih->pmurev >= 2)
5192 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_PLL_PLLCTL_UPD);
5197 si_pmu_pll_on(sih, osh, cc, min_mask, max_mask, clk_ctl_st);
5208 BCMATTACHFN(si_pmu1_pllinit0)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 xtal)
5223 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++)
5238 if ((((R_REG(osh, PMUREG(sih, pmucontrol)) & PCTL_XTALFREQ_MASK) >>
5240 !((CHIPID(sih->chip) == BCM4319_CHIP_ID) || (CHIPID(sih->chip) == BCM4330_CHIP_ID)))
5250 switch (CHIPID(sih->chip)) {
5255 AND_REG(osh, PMUREG(sih, min_res_mask),
5257 AND_REG(osh, PMUREG(sih, max_res_mask),
5265 AND_REG(osh, PMUREG(sih, min_res_mask),
5267 AND_REG(osh, PMUREG(sih, max_res_mask),
5271 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL4);
5280 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5281 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL5);
5282 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data)) & PMU1_PLL0_PC5_CLK_DRV_MASK;
5287 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5293 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4315_HT_AVAIL)));
5294 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4315_HT_AVAIL)));
5297 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
5298 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4315_BBPLL_PWRSW_PU)));
5314 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4319_HT_AVAIL)));
5315 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4319_HT_AVAIL)));
5318 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
5319 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
5324 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL4);
5326 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5331 AND_REG(osh, PMUREG(sih, min_res_mask),
5333 AND_REG(osh, PMUREG(sih, max_res_mask),
5341 AND_REG(osh, PMUREG(sih, min_res_mask),
5343 AND_REG(osh, PMUREG(sih, max_res_mask),
5357 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL0);
5358 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data)) &
5362 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5364 if ((CHIPID(sih->chip) == BCM4330_CHIP_ID)) {
5365 if (CHIPREV(sih->chiprev) < 2)
5371 si_pmu_set_4330_plldivs(sih, dacrate);
5374 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && (CHIPREV(sih->chiprev) == 0)) {
5376 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL1);
5377 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5380 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5382 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
5383 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
5384 (CHIPID(sih->chip) == BCM43362_CHIP_ID) ||
5385 (CHIPID(sih->chip) == BCM4330_CHIP_ID))
5391 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL2);
5392 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data)) &
5396 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5399 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL3);
5400 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data)) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
5403 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5409 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL5);
5410 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data)) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
5412 W_REG(osh, PMUREG(sih, pllcontrol_data), tmp);
5420 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) && (xt->fref != XTAL_FREQ_30000MHZ)) {
5421 W_REG(osh, PMUREG(sih, chipcontrol_addr), PMU1_PLL0_CHIPCTL2);
5422 tmp = R_REG(osh, PMUREG(sih, chipcontrol_data)) & ~CCTL_4319USB_XTAL_SEL_MASK;
5428 W_REG(osh, PMUREG(sih, chipcontrol_data), tmp);
5432 if (sih->pmurev >= 2)
5433 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_PLL_PLLCTL_UPD);
5436 tmp = R_REG(osh, PMUREG(sih, pmucontrol)) &
5442 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) && CHIPREV(sih->chiprev) == 0) {
5444 AND_REG(osh, PMUREG(sih, clkstretch), ~CSTRETCH_HT);
5448 W_REG(osh, PMUREG(sih, pmucontrol), tmp);
5456 BCMINITFN(si_pmu1_cpuclk0)(si_t *sih, osl_t *osh, chipcregs_t *cc)
5461 uint32 FVCO = si_pmu1_pllfvco0(sih); /* in [khz] units */
5463 if ((CHIPID(sih->chip) == BCM43602_CHIP_ID ||
5464 CHIPID(sih->chip) == BCM43462_CHIP_ID) &&
5466 (si_arm_clockratio(sih, 0) == 1) &&
5470 return si_pmu_si_clock(sih, osh); /* in [hz] units */
5472 switch (CHIPID(sih->chip)) {
5481 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL1);
5482 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5487 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL2);
5488 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5495 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL1);
5496 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5502 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL1);
5503 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5511 if (CHIPREV(sih->chiprev) >= 3) {
5512 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL2);
5513 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5518 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL1);
5519 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5536 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL5);
5537 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5543 ASSERT(si_arm_clockratio(sih, 0) == 2);
5545 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL5);
5546 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
5551 PMU_MSG(("si_pmu1_cpuclk0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5564 si_mac_clk(si_t *sih, osl_t *osh)
5571 uint32 FVCO = si_pmu1_pllfvco0(sih); /* in [khz] units */
5574 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
5578 switch (CHIPID(sih->chip)) {
5580 pll_reg = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
5587 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5593 si_restore_core(sih, origidx, intr_val);
5601 si_pmu_fvco_pllreg(si_t *sih, uint32 *fvco, uint32 *pllreg)
5607 *fvco = si_pmu1_pllfvco0(sih)/1000;
5610 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
5614 switch (CHIPID(sih->chip)) {
5627 *pllreg = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
5631 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8)));
5637 si_restore_core(sih, origidx, intr_val);
5644 si_pmu_is_autoresetphyclk_disabled(si_t *sih, osl_t *osh)
5648 switch (CHIPID(sih->chip)) {
5650 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
5651 if (R_REG(osh, PMUREG(sih, chipcontrol_data)) & 0x00000002)
5663 si_pmu_switch_on_PARLDO(si_t *sih, osl_t *osh)
5667 switch (CHIPID(sih->chip)) {
5670 mask = R_REG(osh, PMUREG(sih, min_res_mask)) | PMURES_BIT(RES43602_PARLDO_PU);
5671 W_REG(osh, PMUREG(sih, min_res_mask), mask);
5672 mask = R_REG(osh, PMUREG(sih, max_res_mask)) | PMURES_BIT(RES43602_PARLDO_PU);
5673 W_REG(osh, PMUREG(sih, max_res_mask), mask);
5684 BCMATTACHFN(si_set_bb_vcofreq_frac)(si_t *sih, osl_t *osh, int vcofreq, int frac, int xtalfreq)
5692 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
5693 (CHIPID(sih->chip) == BCM43460_CHIP_ID) ||
5694 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
5695 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
5696 (CHIPID(sih->chip) == BCM43526_CHIP_ID) ||
5697 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) {
5699 cc = si_setcoreidx(sih, SI_CC_IDX);
5702 if (CHIPID(sih->chip) == BCM4360_CHIP_ID &&
5714 } else if (BCM4350_CHIP(sih->chip) &&
5715 (CST4350_IFC_MODE(sih->chipst) == CST4350_IFC_MODE_PCIE)) {
5738 si_pmu_pllcontrol(sih, 2, pllctrl2_mask, reg);
5747 si_pmu_pllcontrol(sih, 3, pllctrl3_mask, fraca);
5750 si_pmu_pllupd(sih);
5755 si_pmu_get_bb_vcofreq(si_t *sih, osl_t *osh, int xtalfreq)
5764 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
5765 (CHIPID(sih->chip) == BCM43460_CHIP_ID) ||
5766 (CHIPID(sih->chip) == BCM43526_CHIP_ID) ||
5767 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
5768 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
5769 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) {
5770 reg = si_pmu_pllcontrol(sih, 2, 0, 0);
5776 frac = si_pmu_pllcontrol(sih, 3, 0, 0);
5777 } else if (BCM4350_CHIP(sih->chip) &&
5778 (CST4350_IFC_MODE(sih->chipst) == CST4350_IFC_MODE_PCIE)) {
5779 reg = si_pmu_pllcontrol(sih, 2, 0, 0);
5785 frac = si_pmu_pllcontrol(sih, 3, 0, 0) & 0x00ffffff;
5813 si_pmu_enb_slow_clk(si_t *sih, osl_t *osh, uint32 xtalfreq)
5817 if ((sih->buscoretype != PCIE2_CORE_ID) ||
5818 ((sih->buscorerev != 7) &&
5819 (sih->buscorerev != 9) &&
5820 (sih->buscorerev != 11)))
5831 W_REG(osh, PMUREG(sih, slowclkperiod), val);
5842 BCMATTACHFN(si_pmu_pll_init)(si_t *sih, osl_t *osh, uint xtalfreq)
5847 ASSERT(sih->cccaps & CC_CAP_PMU);
5850 origidx = si_coreidx(sih);
5851 cc = si_setcoreidx(sih, SI_CC_IDX);
5854 switch (CHIPID(sih->chip)) {
5856 si_pmu0_pllinit0(sih, osh, cc, xtalfreq);
5861 si_pmu0_pllinit0(sih, osh, cc, xtalfreq);
5864 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
5869 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
5878 if (CHIPREV(sih->chiprev) == 0) {
5881 minmask = R_REG(osh, PMUREG(sih, min_res_mask));
5882 maxmask = R_REG(osh, PMUREG(sih, max_res_mask));
5886 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
5887 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
5889 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
5890 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
5895 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU2_SI_PLL_PLLCTL);
5896 W_REG(osh, PMUREG(sih, pllcontrol_data), 0x380005c0);
5900 W_REG(osh, PMUREG(sih, max_res_mask), maxmask);
5902 W_REG(osh, PMUREG(sih, min_res_mask), minmask);
5912 if (CHIPREV(sih->chiprev) > 2)
5913 si_set_bb_vcofreq_frac(sih, osh, 960, 98, 40);
5918 si_set_bb_vcofreq_frac(sih, osh, 960, 98, 40);
5942 si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
5950 si_pmu1_pllinit1(sih, osh, cc, xtalfreq);
5961 si_pmu1_pllinit1(sih, osh, cc, xtalfreq);
5963 si_set_bb_vcofreq_frac(sih, osh, 968, 0, 40);
5971 si_pmu2_pllinit0(sih, osh, cc, xtalfreq);
5974 si_pmu2_pllinit0(sih, osh, cc, xtalfreq);
5978 bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
5986 si_pmu_enb_slow_clk(sih, osh, xtalfreq);
5989 si_setcoreidx(sih, origidx);
5994 BCMINITFN(si_pmu_alp_clock)(si_t *sih, osl_t *osh)
6000 ASSERT(sih->cccaps & CC_CAP_PMU);
6003 origidx = si_coreidx(sih);
6004 cc = si_setcoreidx(sih, SI_CC_IDX);
6007 switch (CHIPID(sih->chip)) {
6009 clock = si_pmu0_alpclk0(sih, osh, cc);
6012 clock = si_pmu0_alpclk0(sih, osh, cc);
6015 clock = si_pmu1_alpclk0(sih, osh, cc);
6021 if (sih->chipst & CST4360_XTAL_40MZ)
6080 clock = si_pmu1_alpclk0(sih, osh, cc);
6087 clock = si_pmu2_alpclk0(sih, osh, cc);
6097 bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev, clock));
6102 si_setcoreidx(sih, origidx);
6111 BCMINITFN(si_pmu5_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
6127 if ((CHIPID(sih->chip) == BCM5357_CHIP_ID) ||
6128 (CHIPID(sih->chip) == BCM4749_CHIP_ID)) {
6135 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_P1P2_OFF);
6136 (void)R_REG(osh, PMUREG(sih, pllcontrol_addr));
6137 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
6141 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_M14_OFF);
6142 (void)R_REG(osh, PMUREG(sih, pllcontrol_addr));
6143 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
6146 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU5_PLL_NM5_OFF);
6147 (void)R_REG(osh, PMUREG(sih, pllcontrol_addr));
6148 tmp = R_REG(osh, PMUREG(sih, pllcontrol_data));
6152 fc = si_pmu_alp_clock(sih, osh) / 1000000;
6163 BCMINITFN(si_4706_pmu_clock)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m)
6175 W_REG(osh, PMUREG(sih, pllcontrol_addr), pll0 + PMU6_4706_PROCPLL_OFF);
6176 w = R_REG(NULL, PMUREG(sih, pllcontrol_data));
6201 BCMINITFN(si_pmu_si_clock)(si_t *sih, osl_t *osh)
6207 ASSERT(sih->cccaps & CC_CAP_PMU);
6210 origidx = si_coreidx(sih);
6211 cc = si_setcoreidx(sih, SI_CC_IDX);
6214 switch (CHIPID(sih->chip)) {
6216 clock = si_pmu0_cpuclk0(sih, osh, cc);
6222 clock = si_pmu1_cpuclk0(sih, osh, cc);
6241 clock = si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0, PMU5_MAINPLL_SI);
6244 if (CHIPREV(sih->chiprev) == 0)
6247 clock = si_pmu1_cpuclk0(sih, osh, cc);
6273 clock = si_pmu1_cpuclk0(sih, osh, cc);
6279 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU1_PLL0_PLLCTL4);
6280 mdiv = (R_REG(osh, PMUREG(sih, pllcontrol_data)) &
6282 clock = si_pmu1_pllfvco0(sih) / mdiv * 1000;
6294 clock = si_pmu2_cpuclk0(sih, osh, cc);
6302 clock = si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0, PMU5_MAINPLL_SI);
6306 clock = si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0, PMU5_MAINPLL_SI);
6312 clock = si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_SI);
6317 bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev, clock));
6322 si_setcoreidx(sih, origidx);
6328 BCMINITFN(si_pmu_cpu_clock)(si_t *sih, osl_t *osh)
6334 ASSERT(sih->cccaps & CC_CAP_PMU);
6337 if (CHIPID(sih->chip) == BCM5354_CHIP_ID)
6340 if (CHIPID(sih->chip) == BCM53572_CHIP_ID)
6343 if ((sih->pmurev >= 5) &&
6344 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
6345 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
6346 (CHIPID(sih->chip) == BCM43234_CHIP_ID) ||
6347 (CHIPID(sih->chip) == BCM43235_CHIP_ID) ||
6348 (CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
6349 (CHIPID(sih->chip) == BCM43238_CHIP_ID) ||
6350 (CHIPID(sih->chip) == BCM43237_CHIP_ID) ||
6351 (CHIPID(sih->chip) == BCM43239_CHIP_ID) ||
6352 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
6353 (CHIPID(sih->chip) == BCM43362_CHIP_ID) ||
6354 (CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
6355 (CHIPID(sih->chip) == BCM43142_CHIP_ID) ||
6356 (CHIPID(sih->chip) == BCM43143_CHIP_ID) ||
6357 (CHIPID(sih->chip) == BCM43341_CHIP_ID) ||
6358 (CHIPID(sih->chip) == BCM4334_CHIP_ID) ||
6359 (CHIPID(sih->chip) == BCM4324_CHIP_ID) ||
6360 (CHIPID(sih->chip) == BCM43242_CHIP_ID) ||
6361 (CHIPID(sih->chip) == BCM43243_CHIP_ID) ||
6362 (CHIPID(sih->chip) == BCM4330_CHIP_ID) ||
6363 (CHIPID(sih->chip) == BCM4360_CHIP_ID) ||
6364 (CHIPID(sih->chip) == BCM4352_CHIP_ID) ||
6365 (CHIPID(sih->chip) == BCM43526_CHIP_ID) ||
6366 (CHIPID(sih->chip) == BCM43460_CHIP_ID) ||
6367 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
6368 BCM4350_CHIP(sih->chip) ||
6369 (CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
6373 switch (CHIPID(sih->chip)) {
6387 origidx = si_coreidx(sih);
6388 cc = si_setcoreidx(sih, SI_CC_IDX);
6391 if (CHIPID(sih->chip) == BCM4706_CHIP_ID)
6392 clock = si_4706_pmu_clock(sih, osh, cc,
6394 else if (CHIPID(sih->chip) == BCM43602_CHIP_ID ||
6395 CHIPID(sih->chip) == BCM43462_CHIP_ID)
6396 clock = si_pmu1_cpuclk0(sih, osh, cc);
6398 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
6401 si_setcoreidx(sih, origidx);
6403 clock = si_pmu_si_clock(sih, osh);
6410 BCMINITFN(si_pmu_mem_clock)(si_t *sih, osl_t *osh)
6416 ASSERT(sih->cccaps & CC_CAP_PMU);
6418 if (CHIPID(sih->chip) == BCM53572_CHIP_ID)
6421 if ((sih->pmurev >= 5) &&
6422 !((CHIPID(sih->chip) == BCM4329_CHIP_ID) ||
6423 (CHIPID(sih->chip) == BCM4319_CHIP_ID) ||
6424 (CHIPID(sih->chip) == BCM4330_CHIP_ID) ||
6425 (CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
6426 (CHIPID(sih->chip) == BCM43142_CHIP_ID) ||
6427 (CHIPID(sih->chip) == BCM43143_CHIP_ID) ||
6428 (CHIPID(sih->chip) == BCM43341_CHIP_ID) ||
6429 (CHIPID(sih->chip) == BCM4334_CHIP_ID) ||
6430 (CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
6431 (CHIPID(sih->chip) == BCM43362_CHIP_ID) ||
6432 (CHIPID(sih->chip) == BCM43234_CHIP_ID) ||
6433 (CHIPID(sih->chip) == BCM43235_CHIP_ID) ||
6434 (CHIPID(sih->chip) == BCM43236_CHIP_ID) ||
6435 (CHIPID(sih->chip) == BCM43238_CHIP_ID) ||
6436 (CHIPID(sih->chip) == BCM43237_CHIP_ID) ||
6437 (CHIPID(sih->chip) == BCM43239_CHIP_ID) ||
6438 (CHIPID(sih->chip) == BCM4324_CHIP_ID) ||
6439 (CHIPID(sih->chip) == BCM43242_CHIP_ID) ||
6440 (CHIPID(sih->chip) == BCM43243_CHIP_ID) ||
6441 (CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
6442 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
6443 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
6444 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
6445 BCM4350_CHIP(sih->chip) ||
6449 switch (CHIPID(sih->chip)) {
6463 origidx = si_coreidx(sih);
6464 cc = si_setcoreidx(sih, SI_CC_IDX);
6467 if (CHIPID(sih->chip) == BCM4706_CHIP_ID)
6468 clock = si_4706_pmu_clock(sih, osh, cc,
6471 clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
6474 si_setcoreidx(sih, origidx);
6476 clock = si_pmu_si_clock(sih, osh);
6500 BCMINITFN(si_pmu_ilp_clock)(si_t *sih, osl_t *osh)
6502 if (ISSIM_ENAB(sih))
6507 start = R_REG(osh, PMUREG(sih, pmutimer));
6508 if (start != R_REG(osh, PMUREG(sih, pmutimer)))
6509 start = R_REG(osh, PMUREG(sih, pmutimer));
6511 end = R_REG(osh, PMUREG(sih, pmutimer));
6512 if (end != R_REG(osh, PMUREG(sih, pmutimer)))
6513 end = R_REG(osh, PMUREG(sih, pmutimer));
6630 BCMINITFN(si_sdiod_drive_strength_init)(si_t *sih, osl_t *osh, uint32 drivestrength)
6638 if (!(sih->cccaps & CC_CAP_PMU)) {
6642 switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
6657 if (sih->pmurev == 8) {
6660 else if (sih->pmurev == 11) {
6696 bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
6713 W_REG(osh, PMUREG(sih, chipcontrol_addr), PMU_CHIPCTL1);
6714 cc_data_temp = R_REG(osh, PMUREG(sih, chipcontrol_data));
6717 W_REG(osh, PMUREG(sih, chipcontrol_data), cc_data_temp);
6719 W_REG(osh, PMUREG(sih, chipcontrol_addr), str_ovr_pmuctl);
6720 OR_REG(osh, PMUREG(sih, chipcontrol_data), str_ovr_pmuval);
6729 BCMATTACHFN(si_pmu_init)(si_t *sih, osl_t *osh)
6731 ASSERT(sih->cccaps & CC_CAP_PMU);
6733 if (sih->pmurev == 1)
6734 AND_REG(osh, PMUREG(sih, pmucontrol), ~PCTL_NOILP_ON_WAIT);
6735 else if (sih->pmurev >= 2)
6736 OR_REG(osh, PMUREG(sih, pmucontrol), PCTL_NOILP_ON_WAIT);
6738 switch (CHIPID(sih->chip)) {
6740 if (CHIPREV(sih->chiprev) == 2) {
6742 W_REG(osh, PMUREG(sih, regcontrol_addr), 2);
6743 OR_REG(osh, PMUREG(sih, regcontrol_data), 0x100);
6745 W_REG(osh, PMUREG(sih, regcontrol_addr), 3);
6746 OR_REG(osh, PMUREG(sih, regcontrol_data), 0x4);
6751 OR_REG(osh, PMUREG(sih, pmucontrol_ext), 1 << PCTLEX_FTE_SHIFT);
6760 OR_REG(osh, PMUREG(sih, pmucontrol_ext), 1 << PCTLEX_FTE_SHIFT);
6770 if (CHIPREV(sih->chiprev) > 2)
6771 OR_REG(osh, PMUREG(sih, pmucontrol_ext), 1 << PCTLEX_FTE_SHIFT);
6780 BCMINITFN(si_pmu_res_uptime)(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 rsrc)
6790 W_REG(osh, PMUREG(sih, res_table_sel), rsrc);
6791 if (sih->pmurev >= 13)
6792 uptime = (R_REG(osh, PMUREG(sih, res_updn_timer)) >> 16) & 0x3ff;
6794 uptime = (R_REG(osh, PMUREG(sih, res_updn_timer)) >> 8) & 0xff;
6797 deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), FALSE);
6801 deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), TRUE);
6804 si_pmu_res_masks(sih, &min_mask, &max_mask);
6816 dup = si_pmu_res_uptime(sih, osh, cc, (uint8)i);
6829 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, bool all)
6837 W_REG(osh, PMUREG(sih, res_table_sel), i);
6838 deps |= R_REG(osh, PMUREG(sih, res_dep_mask));
6841 return !all ? deps : (deps ? (deps | si_pmu_res_deps(sih, osh, cc, deps, TRUE)) : 0);
6850 si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask)
6857 ASSERT(sih->cccaps & CC_CAP_PMU);
6860 if (si_is_otp_disabled(sih)) {
6866 origidx = si_coreidx(sih);
6867 cc = si_setcoreidx(sih, SI_CC_IDX);
6876 if (sih->ccrev == 45) {
6885 si_setcoreidx(sih, origidx);
6889 switch (CHIPID(sih->chip)) {
6923 rsc = si_pmu_get_rsc_positions(sih);
6937 min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
6941 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, TRUE);
6945 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
6946 si_pmu_wait_for_steady_state(sih, osh, cc);
6948 SPINWAIT(!(R_REG(osh, PMUREG(sih, res_state)) & rsrcs),
6950 ASSERT(R_REG(osh, PMUREG(sih, res_state)) & rsrcs);
6960 min_mask = R_REG(osh, PMUREG(sih, min_res_mask));
6967 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, TRUE);
6971 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
6972 si_pmu_wait_for_steady_state(sih, osh, cc);
6983 si_setcoreidx(sih, origidx);
6988 si_pmu_rcal(si_t *sih, osl_t *osh)
6994 ASSERT(sih->cccaps & CC_CAP_PMU);
6997 origidx = si_coreidx(sih);
6998 cc = si_setcoreidx(sih, SI_CC_IDX);
7001 switch (CHIPID(sih->chip)) {
7007 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7010 AND_REG(osh, PMUREG(sih, chipcontrol_data), ~0x04);
7023 OR_REG(osh, PMUREG(sih, chipcontrol_data), 0x04);
7040 W_REG(osh, PMUREG(sih, regcontrol_addr), 0);
7041 val = R_REG(osh, PMUREG(sih, regcontrol_data)) & ~((uint32)0x07 << 29);
7043 W_REG(osh, PMUREG(sih, regcontrol_data), val);
7044 W_REG(osh, PMUREG(sih, regcontrol_addr), 1);
7045 val = R_REG(osh, PMUREG(sih, regcontrol_data)) & ~(uint32)0x01;
7047 W_REG(osh, PMUREG(sih, regcontrol_data), val);
7050 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7051 val = R_REG(osh, PMUREG(sih, chipcontrol_data)) & ~((uint32)0x03 << 30);
7053 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
7054 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7055 val = R_REG(osh, PMUREG(sih, chipcontrol_data)) & ~(uint32)0x03;
7057 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
7060 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7061 OR_REG(osh, PMUREG(sih, chipcontrol_data), (0x01 << 29));
7064 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7065 AND_REG(osh, PMUREG(sih, chipcontrol_data), ~0x04);
7074 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7077 AND_REG(osh, PMUREG(sih, chipcontrol_data), ~0x04);
7080 OR_REG(osh, PMUREG(sih, chipcontrol_data), 0x04);
7093 W_REG(osh, PMUREG(sih, regcontrol_addr), 0);
7094 val = R_REG(osh, PMUREG(sih, regcontrol_data)) & ~((uint32)0x07 << 29);
7096 W_REG(osh, PMUREG(sih, regcontrol_data), val);
7097 W_REG(osh, PMUREG(sih, regcontrol_addr), 1);
7098 val = R_REG(osh, PMUREG(sih, regcontrol_data)) & ~(uint32)0x01;
7100 W_REG(osh, PMUREG(sih, regcontrol_data), val);
7103 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7104 val = R_REG(osh, PMUREG(sih, chipcontrol_data)) & ~((uint32)0x03 << 30);
7106 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
7107 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7108 val = R_REG(osh, PMUREG(sih, chipcontrol_data)) & ~(uint32)0x03;
7110 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
7113 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7114 OR_REG(osh, PMUREG(sih, chipcontrol_data), (0x01 << 29));
7117 W_REG(osh, PMUREG(sih, chipcontrol_addr), 1);
7118 AND_REG(osh, PMUREG(sih, chipcontrol_data), ~0x04);
7127 si_setcoreidx(sih, origidx);
7132 si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid)
7139 ASSERT(CHIPID(sih->chip) != BCM43143_CHIP_ID); /* LCN40 PHY */
7142 if ((CHIPID(sih->chip) == BCM4324_CHIP_ID) && (CHIPREV(sih->chiprev) <= 2)) {
7146 if ((CHIPID(sih->chip) == BCM43242_CHIP_ID) || (CHIPID(sih->chip) == BCM43243_CHIP_ID)) {
7151 if ((CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
7152 (CHIPID(sih->chip) == BCM43362_CHIP_ID) ||
7153 (CHIPID(sih->chip) == BCM43239_CHIP_ID) ||
7154 (CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
7155 (CHIPID(sih->chip) == BCM43142_CHIP_ID) ||
7156 (CHIPID(sih->chip) == BCM4334_CHIP_ID) ||
7157 (CHIPID(sih->chip) == BCM43242_CHIP_ID) ||
7158 (CHIPID(sih->chip) == BCM43243_CHIP_ID) ||
7159 (CHIPID(sih->chip) == BCM43341_CHIP_ID) ||
7160 (CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
7161 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
7162 (CHIPID(sih->chip) == BCM4330_CHIP_ID))
7168 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
7173 si_pmu_pll_off(sih, osh, cc, &min_res_mask, &max_res_mask, &clk_ctl_st);
7176 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
7180 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
7183 si_restore_core(sih, origidx, intr_val);
7189 si_pmu_spuravoid_isdone(si_t *sih, osl_t *osh, uint32 min_res_mask,
7197 ASSERT(CHIPID(sih->chip) != BCM43143_CHIP_ID); /* LCN40 PHY */
7200 if ((CHIPID(sih->chip) == BCM4324_CHIP_ID) && (CHIPREV(sih->chiprev) <= 2)) {
7204 if ((CHIPID(sih->chip) == BCM43242_CHIP_ID) || (CHIPID(sih->chip) == BCM43243_CHIP_ID)) {
7209 if ((CHIPID(sih->chip) == BCM4336_CHIP_ID) ||
7210 (CHIPID(sih->chip) == BCM43362_CHIP_ID) ||
7211 (CHIPID(sih->chip) == BCM43239_CHIP_ID) ||
7212 (CHIPID(sih->chip) == BCM4314_CHIP_ID) ||
7213 (CHIPID(sih->chip) == BCM43142_CHIP_ID) ||
7214 (CHIPID(sih->chip) == BCM4334_CHIP_ID) ||
7215 (CHIPID(sih->chip) == BCM43242_CHIP_ID) ||
7216 (CHIPID(sih->chip) == BCM43243_CHIP_ID) ||
7217 (CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
7218 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
7219 (CHIPID(sih->chip) == BCM4330_CHIP_ID))
7224 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
7228 si_pmu_pll_off_isdone(sih, osh, cc);
7230 si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
7234 si_pmu_pll_on(sih, osh, cc, min_res_mask, max_res_mask, clk_ctl_st);
7237 si_restore_core(sih, origidx, intr_val);
7275 si_pmu_pllctrl_spurupdate(si_t *sih, osl_t *osh, chipcregs_t *cc, uint8 spuravoid,
7281 W_REG(osh, PMUREG(sih, pllcontrol_addr), pllctrl_spur[indx].pllctrl_reg);
7282 W_REG(osh, PMUREG(sih, pllcontrol_data), pllctrl_spur[indx].pllctrl_regval);
7288 si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, uint8 spuravoid)
7294 uint32 *pllctrl_addr = PMUREG(sih, pllcontrol_addr);
7295 uint32 *pllctrl_data = PMUREG(sih, pllcontrol_data);
7297 ASSERT(CHIPID(sih->chip) != BCM43143_CHIP_ID); /* LCN40 PHY */
7299 switch (CHIPID(sih->chip)) {
7305 si_pmu_pllctrl_spurupdate(sih, osh, cc, spuravoid, spuravoid_4324,
7318 if ((CHIPID(sih->chip) == BCM6362_CHIP_ID) && (sih->chiprev == 0)) {
7350 const uint8 phypll_offset = ((CHIPID(sih->chip) == BCM5357_CHIP_ID) ||
7351 (CHIPID(sih->chip) == BCM4749_CHIP_ID) ||
7352 (CHIPID(sih->chip) == BCM53572_CHIP_ID))
7381 if (ISSIM_ENAB(sih)) {
7552 xtal_freq = si_alp_clock(sih)/1000;
7554 for (params_tbl = si_pmu1_xtaltab0(sih);
7560 params_tbl = si_pmu1_xtaldef0(sih);
7639 xtal_freq = si_pmu_alp_clock(sih, osh)/1000;
7709 xtal_freq = si_pmu_alp_clock(sih, osh) / 1000;
7716 __FUNCTION__, bcm_chipname(sih->chip, chn, 8)));
7720 tmp |= R_REG(osh, PMUREG(sih, pmucontrol));
7721 W_REG(osh, PMUREG(sih, pmucontrol), tmp);
7725 si_pmu_cal_fvco(si_t *sih, osl_t *osh)
7734 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
7738 xf = si_pmu_alp_clock(sih, osh)/1000;
7740 pll_reg = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, 0, 0);
7748 pll_reg = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL3, 0, 0);
7779 si_restore_core(sih, origidx, intr_val);
7785 si_pmu_gband_spurwar(si_t *sih, osl_t *osh)
7792 if ((CHIPID(sih->chip) == BCM43222_CHIP_ID) ||
7793 (CHIPID(sih->chip) == BCM43420_CHIP_ID)) {
7795 cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
7802 minmask = R_REG(osh, PMUREG(sih, min_res_mask));
7803 maxmask = R_REG(osh, PMUREG(sih, max_res_mask));
7807 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
7808 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_HT_SI_AVAIL)));
7810 AND_REG(osh, PMUREG(sih, min_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
7811 AND_REG(osh, PMUREG(sih, max_res_mask), ~(PMURES_BIT(RES4322_SI_PLL_ON)));
7816 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU2_PLL_PLLCTL2);
7817 W_REG(osh, PMUREG(sih, pllcontrol_data), (R_REG(osh, PMUREG(sih, pllcontrol_data)) &
7824 W_REG(osh, PMUREG(sih, pllcontrol_addr), PMU2_PLL_PLLCTL5);
7825 W_REG(osh, PMUREG(sih, pllcontrol_data), (R_REG(osh, PMUREG(sih, pllcontrol_data)) &
7835 W_REG(osh, PMUREG(sih, pmucontrol), R_REG(osh, PMUREG(sih, pmucontrol)) |
7840 W_REG(osh, PMUREG(sih, max_res_mask), maxmask);
7842 W_REG(osh, PMUREG(sih, min_res_mask), minmask);
7852 si_restore_core(sih, origidx, intr_val);
7857 si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
7865 idx = si_coreidx(sih);
7866 cc = si_setcoreidx(sih, SI_CC_IDX);
7869 si_pmu_wait_for_steady_state(sih, osh, cc);
7871 switch (CHIPID(sih->chip)) {
7907 rsc = si_pmu_get_rsc_positions(sih);
7908 st = (R_REG(osh, PMUREG(sih, res_state)) & PMURES_BIT(rsc->otp_pu)) != 0;
7930 si_setcoreidx(sih, idx);
7936 si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
7938 BCMATTACHFN(si_pmu_sprom_enable)(si_t *sih, osl_t *osh, bool enable)
7941 switch (CHIPID(sih->chip)) {
7943 if (CHIPREV(sih->chiprev) < 1)
7945 if (sih->chipst & CST4315_SPROM_SEL) {
7947 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7948 val = R_REG(osh, PMUREG(sih, chipcontrol_data));
7953 W_REG(osh, PMUREG(sih, chipcontrol_data), val);
7963 si_pmu_is_sprom_enabled(si_t *sih, osl_t *osh)
7965 BCMATTACHFN(si_pmu_is_sprom_enabled)(si_t *sih, osl_t *osh)
7970 switch (CHIPID(sih->chip)) {
7972 if (CHIPREV(sih->chiprev) < 1)
7974 if (!(sih->chipst & CST4315_SPROM_SEL))
7976 W_REG(osh, PMUREG(sih, chipcontrol_addr), 0);
7977 if (R_REG(osh, PMUREG(sih, chipcontrol_data)) & 0x80000000)
7991 BCMATTACHFN(si_pmu_set_lpoclk)(si_t *sih, osl_t *osh)
8007 switch (CHIPID(sih->chip)) {
8011 si_pmu_regcontrol(sih, CHIPCTRLREG2, PMU43602_CC2_XTAL32_SEL,
8016 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_EXT_LPO_PU, CC_EXT_LPO_PU);
8017 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_EXT_LPO_PU, GC_EXT_LPO_PU);
8021 ext_lpo_avail = R_REG(osh, PMUREG(sih, pmustatus)) & EXT_LPO_AVAIL;
8024 ext_lpo_avail = R_REG(osh, PMUREG(sih, pmustatus)) & EXT_LPO_AVAIL;
8035 switch (CHIPID(sih->chip)) {
8038 si_pmu_regcontrol(sih, CHIPCTRLREG2, PMU43602_CC2_FORCE_EXT_LPO,
8043 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, EXT_LPO_SEL);
8045 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0);
8048 lpo_sel = R_REG(osh, PMUREG(sih, pmucontrol)) & LPO_SEL;
8051 lpo_sel = R_REG(osh, PMUREG(sih, pmucontrol)) & LPO_SEL;
8059 switch (CHIPID(sih->chip)) {
8062 si_pmu_regcontrol(sih, CHIPCTRLREG2,
8066 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0);
8071 switch (CHIPID(sih->chip)) {
8076 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_INT_LPO_PU, 0x0);
8077 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_INT_LPO_PU, 0x0);
8083 switch (CHIPID(sih->chip)) {
8089 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_INT_LPO_PU, CC_INT_LPO_PU);
8090 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_INT_LPO_PU, GC_INT_LPO_PU);
8095 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, INT_LPO_SEL);
8097 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0);
8101 lpo_sel = R_REG(osh, PMUREG(sih, pmucontrol)) & LPO_SEL;
8105 lpo_sel = R_REG(osh, PMUREG(sih, pmucontrol)) & LPO_SEL;
8111 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0);
8114 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_EXT_LPO_PU, 0x0);
8115 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_EXT_LPO_PU, 0x0);
8124 BCMATTACHFN(si_pmu_chip_init)(si_t *sih, osl_t *osh)
8126 ASSERT(sih->cccaps & CC_CAP_PMU);
8128 si_pmu_otp_chipcontrol(sih, osh);
8131 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);
8136 si_pmu_sprom_enable(sih, osh, FALSE);
8140 switch (CHIPID(sih->chip)) {
8143 si_setcore(sih, PCMCIA_CORE_ID, 0);
8144 si_core_disable(sih, 0);
8153 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8156 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU4324_CC2_SDIO_AOS_EN,
8161 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8164 si_pmu_chipcontrol(sih, PMU_CHIPCTL2,
8175 si_pmu_chipcontrol(sih, 4, 0x1f0000, 0x140000);
8181 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, PMU4324_CC1_GPIO_CONF_MASK, 0x2);
8198 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, mask, val);
8208 W_REG(osh, PMUREG(sih, chipcontrol_addr), PMU_CHIPCTL3);
8209 tmp = R_REG(osh, PMUREG(sih, chipcontrol_data));
8212 W_REG(osh, PMUREG(sih, chipcontrol_data), tmp);
8229 if (CST4350_IFC_MODE(sih->chipst) == CST4350_IFC_MODE_PCIE) {
8231 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8233 si_pmu_regcontrol(sih, 0, ~0, 1);
8236 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, CC5_4350_PMU_EN_ASSERT_MASK,
8240 if ((CHIPID(sih->chip) == BCM4350_CHIP_ID) &&
8241 (sih->chiprev == 0)) { /* 4350A0 */
8246 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, val, val);
8250 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, val, val);
8254 si_pmu_set_lpoclk(sih, osh);
8261 si_pmu_set_lpoclk(sih, osh);
8269 si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh)
8276 if (!PMUCTL_ENAB(sih))
8279 origidx = si_coreidx(sih);
8280 cc = si_setcoreidx(sih, SI_CC_IDX);
8286 switch (CHIPID(sih->chip)) {
8308 mode = CST4350_IFC_MODE(sih->chipst);
8318 if (((CHIPREV(sih->chiprev) >= 3) ||
8319 (CHIPID(sih->chip) == BCM4354_CHIP_ID) ||
8320 (CHIPID(sih->chip) == BCM4356_CHIP_ID) ||
8321 (CHIPID(sih->chip) == BCM43569_CHIP_ID) ||
8322 (CHIPID(sih->chip) == BCM43570_CHIP_ID)) &&
8323 CST4350_PKG_USB_40M(sih->chipst) &&
8324 CST4350_PKG_USB(sih->chipst)) {
8336 xtalfreq = si_pmu_measure_alpclk(sih, osh);
8337 si_pmu_enb_slow_clk(sih, osh, xtalfreq);
8339 si_setcoreidx(sih, origidx);
8356 BCMATTACHFN(si_pmu_swreg_init)(si_t *sih, osl_t *osh)
8361 ASSERT(sih->cccaps & CC_CAP_PMU);
8363 switch (CHIPID(sih->chip)) {
8365 if (CHIPREV(sih->chiprev) < 3)
8367 if (((sih->chipst & CST4325_PMUTOP_2B_MASK) >> CST4325_PMUTOP_2B_SHIFT) == 1) {
8369 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xf);
8371 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, 0xf);
8374 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0xb);
8376 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0xb);
8378 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0x1);
8380 if (sih->boardflags & BFL_LNLDO2_2P5)
8381 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO2_SEL, 0x1);
8385 if (CHIPREV(sih->chiprev) != 2)
8388 W_REG(osh, PMUREG(sih, regcontrol_addr), 4);
8389 val = R_REG(osh, PMUREG(sih, regcontrol_data));
8391 W_REG(osh, PMUREG(sih, regcontrol_data), val);
8395 if (CHIPREV(sih->chiprev) < 2) {
8397 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
8399 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST, 0xe);
8401 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
8403 if (CHIPREV(sih->chiprev) == 2) {
8405 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0x16);
8407 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0x16);
8408 si_pmu_set_ldo_voltage(sih, osh, SET_LNLDO_PWERUP_LATCH_CTRL, 0x3);
8410 if (CHIPREV(sih->chiprev) == 0)
8411 si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
8420 vreg_val = si_pmu_cbuckout_to_vreg_ctrl(sih, cbuck_mv);
8423 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, vreg_val);
8424 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, vreg_val);
8428 if (CHIPREV(sih->chiprev) == 0) {
8430 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LDO2, 0);
8440 si_pmu_regcontrol(sih, PMU_VREG0_ADDR, (1 << PMU_VREG0_DISABLE_PULLD_BT_SHIFT) |
8443 if (!CST4334_CHIPMODE_HSIC(sih->chipst))
8444 si_pmu_chipcontrol(sih, 2, CCTRL4334_HSIC_LDO_PU, CCTRL4334_HSIC_LDO_PU);
8449 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LDO2, (uint8) cldo);
8454 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LDO2, 0);
8459 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, (uint8) cldo);
8465 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr,
8467 pmu_corereg(sih, SI_CC_IDX, regcontrol_data,
8475 si_pmu_regcontrol(sih, 0, 0x2, 0x2);
8477 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0x2);
8478 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_BURST, 0x2);
8480 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0x7);
8482 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, PMU43143_XTAL_CORE_SIZE_MASK, 0x10);
8489 si_gci_chipcontrol(sih, 5, 0x3 << 29, 0x3 << 29);
8506 if (CHIPREV(sih->chiprev) == 3)
8507 si_gci_chipcontrol(sih, 5, 0x3 << 29, 0x3 << 29);
8512 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_PAREF, 0x0c);
8523 if (otp_read_word(sih, OTP4345_AVS_RO_OFFSET, &avs_status) != BCME_OK)
8528 if (otp_read_word(sih, OTP4345_AVS_RO_OFFSET,
8536 si_gci_chipcontrol(sih, CHIPCTRLREG3, CC4345_GCI_AVS_CTRL_MASK,
8546 si_pmu_otp_regcontrol(sih, osh);
8550 si_pmu_radio_enable(si_t *sih, bool enable)
8552 ASSERT(sih->cccaps & CC_CAP_PMU);
8554 switch (CHIPID(sih->chip)) {
8556 if (sih->boardflags & BFL_FASTPWR)
8559 if ((sih->boardflags & BFL_BUCKBOOST)) {
8560 pmu_corereg(sih, SI_CC_IDX, min_res_mask,
8575 wrap_reg = si_wrapperreg(sih, AI_OOBSELOUTB74, 0, 0);
8582 si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, wrap_reg);
8593 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk, uint32 delay_val)
8595 ASSERT(sih->cccaps & CC_CAP_PMU);
8598 SPINWAIT(((R_REG(osh, PMUREG(sih, pmustatus)) & clk) != clk), delay_val);
8599 return (R_REG(osh, PMUREG(sih, pmustatus)) & clk);
8610 BCMATTACHFN(si_pmu_measure_alpclk)(si_t *sih, osl_t *osh)
8615 if (sih->pmurev < 10)
8618 ASSERT(sih->cccaps & CC_CAP_PMU);
8619 if ((CHIPID(sih->chip) == BCM4335_CHIP_ID) ||
8620 (CHIPID(sih->chip) == BCM4345_CHIP_ID) ||
8621 (CHIPID(sih->chip) == BCM43602_CHIP_ID) ||
8622 (CHIPID(sih->chip) == BCM43462_CHIP_ID) ||
8623 BCM4350_CHIP(sih->chip) ||
8625 pmustat_lpo = !(R_REG(osh, PMUREG(sih, pmucontrol)) & PCTL_LPO_SEL);
8627 pmustat_lpo = R_REG(osh, PMUREG(sih, pmustatus)) & PST_EXTLPOAVAIL;
8633 W_REG(osh, PMUREG(sih, pmu_xtalfreq), 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
8639 ilp_ctr = R_REG(osh, PMUREG(sih, pmu_xtalfreq)) & PMU_XTALFREQ_REG_ILPCTR_MASK;
8642 W_REG(osh, PMUREG(sih, pmu_xtalfreq), 0);
8655 si_pmu_set_4330_plldivs(si_t *sih, uint8 dacrate)
8657 uint32 FVCO = si_pmu1_pllfvco0(sih)/1000; /* in [Mhz] */
8665 if (CST4330_CHIPMODE_SDIOD(sih->chipst))
8671 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
8673 pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, 0, 0);
8676 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
8690 BCMATTACHFN(si_pmu_cbuckout_to_vreg_ctrl)(si_t *sih, uint16 cbuck_mv)
8703 si_pmu_res_minmax_update(si_t *sih, osl_t *osh)
8705 si_info_t *sii = SI_INFO(sih);
8713 origidx = si_coreidx(sih);
8714 cc = si_setcoreidx(sih, SI_CC_IDX);
8717 switch (CHIPID(sih->chip)) {
8730 si_pmu_res_masks(sih, &min_mask, &max_mask);
8746 min_mask |= si_pmu_res_deps(sih, osh, cc, min_mask, FALSE);
8747 W_REG(osh, PMUREG(sih, min_res_mask), min_mask);
8752 max_mask |= si_pmu_res_deps(sih, osh, cc, max_mask, FALSE);
8753 W_REG(osh, PMUREG(sih, max_res_mask), max_mask);
8756 si_pmu_wait_for_steady_state(sih, osh, cc);
8759 si_setcoreidx(sih, origidx);