Lines Matching refs:si_pmu_chipcontrol
137 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
2439 si_pmu_chipcontrol(sih, 3, 0x1, 0x1);
4274 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (0<<6));
4275 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (1<<6));
4276 si_pmu_chipcontrol(sih, CHIPCTRLREG1, (1<<6), (0<<6));
8016 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_EXT_LPO_PU, CC_EXT_LPO_PU);
8076 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_INT_LPO_PU, 0x0);
8089 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_INT_LPO_PU, CC_INT_LPO_PU);
8114 si_pmu_chipcontrol(sih, CHIPCTRLREG0, CC_EXT_LPO_PU, 0x0);
8153 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8156 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU4324_CC2_SDIO_AOS_EN,
8161 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8164 si_pmu_chipcontrol(sih, PMU_CHIPCTL2,
8175 si_pmu_chipcontrol(sih, 4, 0x1f0000, 0x140000);
8181 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, PMU4324_CC1_GPIO_CONF_MASK, 0x2);
8198 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, mask, val);
8231 si_pmu_chipcontrol(sih, PMU_CHIPCTL1,
8236 si_pmu_chipcontrol(sih, PMU_CHIPCTL5, CC5_4350_PMU_EN_ASSERT_MASK,
8246 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, val, val);
8250 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, val, val);
8444 si_pmu_chipcontrol(sih, 2, CCTRL4334_HSIC_LDO_PU, CCTRL4334_HSIC_LDO_PU);
8482 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, PMU43143_XTAL_CORE_SIZE_MASK, 0x10);