Lines Matching refs:pllctrl_addr
7294 uint32 *pllctrl_addr = PMUREG(sih, pllcontrol_addr);
7321 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7323 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7325 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7327 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7329 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7331 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7334 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7336 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7338 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7340 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7342 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7344 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7362 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0 + phypll_offset);
7369 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2 + phypll_offset);
7383 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7386 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7389 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7394 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7396 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7399 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7401 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7404 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7406 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7416 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7418 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7420 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7422 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7424 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7426 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7429 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7431 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7433 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7435 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7437 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7439 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7448 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7450 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7452 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7454 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7456 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7458 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7461 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7463 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7465 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7467 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7469 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7471 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7482 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7484 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7486 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7488 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7490 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7492 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7495 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7497 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7499 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7501 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7503 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7505 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7516 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7518 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7520 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7524 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7527 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7534 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7536 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7538 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7542 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7545 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7571 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7585 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7589 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7603 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7605 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7607 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7609 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7611 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7613 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7616 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL0);
7618 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL1);
7620 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL2);
7622 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);
7624 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL4);
7626 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL5);
7644 W_REG(osh, pllctrl_addr, PMU15_PLL_PLLCTL0);
7670 W_REG(osh, pllctrl_addr, PMU1_PLL0_PLLCTL3);