Lines Matching refs:ndiv_int
3345 uint8 ndiv_int;
3518 /* fref xf p1div p2div ndiv_int ndiv_frac */
4194 uint32 ndiv_int;
4224 ndiv_int = (fvco * p1div) / xtal;
4226 /* ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 24)) / xtal) */
4227 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 24, 0);
4234 (p1div << 16) | (ndiv_mode << 20) | (ndiv_int << 23);
4244 ndiv_int = (fvco * p1div) / xtal;
4247 * ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 20)) /
4250 bcm_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * ndiv_int, 1 << 20, 0);
4254 PLL_control[6] = (PLL_4345_CONTROL6_DEFAULT & 0xFFFFE000) | p1div | (ndiv_int << 3);
4555 /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
4556 tmp = ((xt->ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT)
5390 /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
5394 tmp |= ((xt->ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) & PMU1_PLL0_PC2_NDIV_INT_MASK) |
5686 uint32 vcofreq_withfrac, p1div, ndiv_int, fraca, ndiv_mode, reg;
5729 ndiv_int = vcofreq / xtalfreq;
5732 vcofreq, xtalfreq, frac, ndiv_mode, ndiv_int));
5734 reg = (ndiv_int << ndiv_int_shift) |
5757 uint32 ndiv_int, /* 9 bits integer divider */
5771 ndiv_int = reg >> 7;
5780 ndiv_int = reg >> 23;
5802 if ((int)xtal1 > (int)((0xffffffff - vcofrac) / ndiv_int)) {
5807 vcofreq = xtal1 * ndiv_int + vcofrac;
7291 uint32 xtal_freq, reg_val, mxdiv, ndiv_int, ndiv_frac_int, part_mul;
7581 ndiv_int = (FCLkx * part_mul * 10)/ (xtal_freq);
7588 | (ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT)));
7727 uint32 xf, ndiv_int, ndiv_frac, fvco, pll_reg, p1_div_scale;
7745 ndiv_int = (pll_reg & PMU4335_PLL0_PC2_NDIV_INT_MASK) >>
7754 /* fvco1 = (100 * (xf * 1/p1_div) * (ndiv_int + (ndiv_frac * 1/(1 << 24)))) */
7759 /* ndiv_int is represented by 9 bits */
7760 /* so (ndiv_int << 24) needs 33 bits */
7765 int_part = xf * ndiv_int;